Spi Interface With Mcbsp Used As Master; Bit Values Required To Configure The Mcbsp As A Spi Master - Texas Instruments Concerto F28M35 Series Technical Reference Manual

SPI Operation Using the Clock Stop Mode
Table 15-16. Bit Values Required to Configure the McBSP as a SPI Master
Required Bit Setting
CLKSTP = 10b or 11b
CLKXP = 0 or 1
CLKRP = 0 or 1
CLKXM = 1
SCLKME = 0
CLKSM = 1
CLKGDV is a value from 1 to 255
FSXM = 1
FSGM = 0
FSXP = 1
XDATDLY = 01b
RDATDLY = 01b
When the McBSP functions as the SPI master, it controls the transmission of data by producing the serial
clock signal. The clock signal on the MCLKX pin is enabled only during packet transfers. When packets
are not being transferred, the MCLKX pin remains high or low depending on the polarity used.
For SPI master operation, the MCLKX pin must be configured as an output. The sample rate generator is
then used to derive the CLKX signal from the CPU clock. The clock stop mode internally connects the
MCLKX pin to the MCLKR signal so that no external signal connection is required on the MCLKR pin and
both the transmit and receive circuits are clocked by the master clock (CLKX).
The data delay parameters of the McBSP (XDATDLY and RDATDLY) must be set to 1 for proper SPI
master operation. A data delay value of 0 or 2 is undefined in the clock stop mode.
The McBSP can also provide a slave-enable signal (SPISTE) on the FSX pin. If a slave-enable signal is
required, the FSX pin must be configured as an output and the transmitter must be configured so that a
frame-synchronization pulse is generated automatically each time a packet is transmitted (FSGM = 0).
The polarity of the FSX pin is programmable high or low; however, in most cases the pin must be
configured active low.
1076
C28 Multichannel Buffered Serial Port (McBSP)
Figure 15-41. SPI Interface with McBSP Used as Master
McBSP master
CLKX
DX
DR
FSX
Description
The clock stop mode (without or with a clock delay) is selected.
The polarity of CLKX as seen on the MCLKX pin is positive (CLKXP = 0) or negative (CLKXP =
1).
The polarity of MCLKR as seen on the MCLKR pin is positive (CLKRP = 0) or negative
(CLKRP = 1).
The MCLKX pin is an output pin driven by the internal sample rate generator. Because
CLKSTP is equal to 10b or 11b, MCLKR is driven internally by CLKX.
The clock generated by the sample rate generator (CLKG) is derived from the CPU clock.
CLKGDV defines the divide down value for CLKG.
The FSX pin is an output pin driven according to the FSGM bit.
The transmitter drives a frame-synchronization pulse on the FSX pin every time data is
transferred from DXR1 to XSR1.
The FSX pin is active low.
This setting provides the correct setup time on the FSX signal.
Copyright © 2012–2019, Texas Instruments Incorporated
SPI-compliant
slave
SPICLK
SPISIMO
SPISOMI
SPISTE
SPRUH22I – April 2012 – Revised November 2019
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