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Register Descriptions
22.6.2 I2C Master Control/Status (I2CMCS), offset 0x004
The I2C Master Control/Status (I2CMCS) register accesses status bits when read and control bits when
written. When read, the status register indicates the state of the I2C bus controller. When written, the
control register configures the I2C controller operation. The first register and description is Read-Only. The
second register and description in this section is Write-Only. They are shown and described in the figures
and tables below.
Figure 22-15. I2C Master Control/Status (I2CMCS) (Read-Only) Register
31
15
7
6
Reserved
BUSBSY
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-4. I2C Master Control/Status (I2CMCS) (Read-Only) Register Field Descriptions
Bit
Field
31-7
Reserved
6
BUSBSY
5
IDLE
4
ARBLST
3
DATACK
2
ADRACK
1
ERROR
0
BUSY
1500
M3 Inter-Integrated Circuit (I2C) Interface
5
4
IDLE
ARBLST
R-0
R-0
Value
Description
Reserved
Bus busy
0
The I2C bus is idle.
1
The I2C bus is busy.
I2C Idle
0
The I2C controller is not idle.
1
The I2C controller is idle.
Arbitration Lost
0
The I2C controller won arbitration.
1
The I2C controller lost arbitration.
Acknowledge Data
0
The transmitted data was acknowledged.
1
The transmitted data was not acknowledged.
Acknowledge Address
0
The transmitted address was acknowledged.
1
The transmitted address was not acknowledged.
Value Description
0
No error was detected on the last operation.
1
An error occurred on the last operation.
I2C Busy
0
The controller is idle.
1
The controller is busy.
Note: When the BUSY bit is set, the other status bits are not valid.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3
2
DATACK
ADRACK
R-0
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
1
0
ERROR
BUSY
R-0
R-0
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