M3 Sx Ram Initdone Register 1 (Msxrinitdone1); M3 Sx Ram Initdone Register 1 (Msxrinitdone1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

RAM Control Module Registers

5.2.1.11 M3 Sx RAM INITDONE Register 1 (MSxRINITDONE1)

31
15 14
Reserved RAMINITDONE
S7
R-0 R-0
7 6
Reserved RAMINITDONE
S3
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-19. M3 Sx RAM INITDONE Register 1 (MSxRINITDONE1) Field Descriptions
Bit Field
31-15 Reserved
14 RAMINITDONES7
13 Reserved
12 RAMINITDONES6
11 Reserved
10 RAMINITDONES5
9 Reserved
8 RAMINITDONES4
7 Reserved
6 RAMINITDONES3
5 Reserved
450
Internal Memory
Figure 5-14. M3 Sx RAM INITDONE Register 1 (MSxRINITDONE1)
13 12
Reserved RAMINITDONE
S6
R-0 R-0
5 4
Reserved RAMINITDONE
S2
R-0 R-0
Value Description
Reserved
RAM Initialization Process Status when RAMINIT is Set for S7 RAM Block
0 RAM initialization is not finished for S7 RAM block.
1 RAM initialization is done for S7 RAM block. S7 RAM can be accessed by M3 CPU/µDMA
or C28x CPU/DMA.
This status bit gets cleared when the RAMINIT bit is set for S7 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for S6 RAM Block
0 RAM initialization is not finished for S6 RAM block.
1 RAM initialization is done for S6 RAM block. S6 RAM can be accessed by M3 CPU/µDMA
or C28x CPU/DMA.
This status bit gets cleared when the RAMINIT bit is set for S6 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for S5 RAM Block
0 RAM initialization is not finished for S5 RAM block.
1 RAM initialization is done for S7\5 RAM block. S5 RAM can be accessed by M3 CPU/µDMA
or C28x CPU/DMA.
This status bit gets cleared when the RAMINIT bit is set for S5 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for S4 RAM Block
0 RAM initialization is not finished for S4 RAM block.
1 RAM initialization is done for S4 RAM block. S4 RAM can be accessed by M3 CPU/µDMA
or C28x CPU/DMA.
This status bit gets cleared when the RAMINIT bit is set for S4 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for S3 RAM Block
0 RAM initialization is not finished for S3 RAM block.
1 RAM initialization is done for S3 RAM block. S3 RAM can be accessed by M3 CPU/µDMA
or C28x CPU/DMA.
This status bit gets cleared when the RAMINIT bit is set for S3 RAM block.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11 10
Reserved RAMINITDONE
S5
R-0 R-0
3 2
Reserved RAMINITDONE
S1
R-0 R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
9 8
Reserved RAMINITDONE
S4
R-0 R-0
1 0
Reserved RAMINITDONE
S0
R-0 R-0
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