Resetting And Enabling The Transmitter; Register Bits Used To Place Transmitter In Reset Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Transmitter Configuration
– Set the transmit DXENA mode.
– Set the transmit interrupt mode.
• Frame-synchronization behavior:
– Set the transmit frame-synchronization mode.
– Set the transmit frame-synchronization polarity.
– Set the SRG frame-synchronization period and pulse width.
• Clock behavior:
– Set the transmit clock mode.
– Set the transmit clock polarity.
– Set the SRG clock divide-down value.
– Set the SRG clock synchronization mode.
– Set the SRG clock mode (choose an input clock).
– Set the SRG input clock polarity.

15.9.2 Resetting and Enabling the Transmitter

The first step of the transmitter configuration procedure is to reset the transmitter, and the last step is to
enable the transmitter (to take it out of reset).
Table 15-47. Register Bits Used to Place Transmitter in Reset Field Descriptions
Register Bit Field
SPCR2 7 FRST
SPCR2 6 GRST
SPCR2 0 XRST
15.9.2.1 Reset Considerations
The serial port can be reset in the following two ways:
1. A DSP reset (XRS signal driven low) places the receiver, transmitter, and sample rate generator in
reset. When the device reset is removed, GRST = FRST = RRST = XRST = 0, keeping the entire
serial port in the reset state.
2. The serial port transmitter and receiver can be reset directly using the RRST and XRST bits in the
serial port control registers. The sample rate generator can be reset directly using the GRST bit in
SPCR2.
3. When using the DMA, the order in which McBSP events must occur is important. DMA channel and
peripheral interrupts must be configured prior to releasing the McBSP transmitter from reset.
The reason for this is that an XRDY is fired when XRST = 1. The XRDY signals the DMA to start
copying data from the buffer into the transmit register. If the McBSP transmitter is released from reset
before the DMA channel and peripheral interrupts are configured, the XRDY signals before the DMA
channel can receive the signal; therefore, the DMA does not move the data from the buffer to the
1098
C28 Multichannel Buffered Serial Port (McBSP)
Table 15-47
Value Description
Frame-synchronization logic reset
0 Frame-synchronization logic is reset. The sample rate generator does not generate frame-
synchronization signal FSG, even if GRST = 1.
1 Frame-synchronization is enabled. If GRST = 1, frame-synchronization signal FSG is
generated after (FPER + 1) number of CLKG clock cycles; all frame counters are loaded
with their programmed values.
Sample rate generator reset
0 Sample rate generator is reset. If GRST = 0 due to a device reset, CLKG is driven by the
CPU clock divided by 2, and FSG is driven low (inactive). If GRST = 0 due to program
code, CLKG and FSG are both driven low (inactive).
1 Sample rate generator is enabled. CLKG is driven according to the configuration
programmed in the sample rate generator registers (SRGR[1,2]). If FRST = 1, the
generator also generates the frame-synchronization signal FSG as programmed in the
sample rate generator registers.
Transmitter reset
0 The serial port transmitter is disabled and in the reset state.
1 The serial port transmitter is enabled.
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describes the bits used for both of these steps.
SPRUH22I – April 2012 – Revised November 2019
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