Uart Control (Uartctl) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 21-10. UART Control (UARTCTL) Register Field Descriptions
Bit Field
31-10 Reserved
9 RXE
8 TXE
7 LBE
6 LIN
5 HSE
4 EOT
3 SMART
2 SIRLP
1 SIREN
0 UARTEN
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Reserved
UART Receive Enable
If the UART is disabled in the middle of a receive, it completes the current character before
stopping.
Note: To enable reception, the UARTEN bit must also be set.
0 The receive section of the UART is disabled.
1 The receive section of the UART is enabled.
UART Transmit Enable
If the UART is disabled in the middle of a transmission, it completes the current character before
stopping.
Note: To enable transmission, the UARTEN bit must also be set.
0 The transmit section of the UART is disabled.
1 The transmit section of the UART is enabled.
UART Loop Back Enable
0 Normal operation.
1 The UnTx path is fed through the UnRx path.
LIN Mode Enable
0 Normal operation.
1 The UART operates in LIN mode.
High-Speed Enable
Note: System clock used is also dependent on the baud-rate divisor configuration (see
Section 21.3.2).
0 The UART is clocked using the system clock divided by 16.
1 The UART is clocked using the system clock divided by 8.
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS register.
0 The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met.
1 The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer.
ISO 7816 Smart Card Support
The application must ensure that it sets 8-bit word length (WLEN set to 0x3) and even parity (PEN
set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is
forced to 2. Note that the UART does not support automatic retransmission on parity errors. If a
parity error is detected on transmission, all further transmit operations are aborted and software
must handle retransmission of the affected byte or message.
0 Normal operation.
1 The UART operates in Smart Card mode.
UART SIR Low-Power Mode
This bit selects the IrDA encoding mode.
Setting this bit uses less power, but might reduce transmission distances. See the UARTILPR
register.
0 Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period.
1 The UART operates in SIR Low-Power mode. Low-level bits are transmitted with a pulse width
which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate.
UART SIR Enable
0 Normal operation.
1 The IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol.
UART Enable
If the UART is disabled in the middle of transmission or reception, it completes the current
character before stopping.
0 The UART is disabled.
1 The UART is enabled.
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M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
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