Pie Interrupts Multiplexing - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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dedicated RAM block that is modifiable. The CPU, upon servicing the interrupt, automatically fetches the

appropriate interrupt vector. It takes nine CPU clock cycles to fetch the vector and save critical CPU

registers. Therefore, the CPU can respond quickly to interrupt events. Prioritization of interrupts is

controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE

By default on power-up or on reset (any reset which can reset the control subsystem CPU), the PIE is

disabled and none of the peripheral interrupts are enabled. However, an NMI and ITRAP exceptions are

enabled by default on power up and a reset occur. When the PIE is disabled, any NMI and ITRAP

exception will use the handlers registered in the ROM vector table, and when the PIE is enabled, an NMI

and ITRAP exceptions will use the handler's registers in the PIE vector table, which is located in PIE RAM.

More details are explained in the following sections.

Overview of the PIE Controller

The 28x CPU supports one nonmaskable interrupt (NMI) and 16 maskable prioritized interrupt requests

(INT1-INT14, RTOSINT, and DLOGINT) at the CPU level. The 28x devices have many peripherals and

each peripheral is capable of generating one or more interrupts in response to many events at the

peripheral level. Because the CPU does not have sufficient capacity to handle all peripheral interrupt

requests at the CPU level, a centralized peripheral interrupt expansion (PIE) controller is required to

arbitrate the interrupt requests from various sources such as peripherals and other external pins. The PIE

vector table is used to store the address (vector) of each interrupt service routine (ISR) within the system.

There is one vector per interrupt source including all MUXed and nonMUXed interrupts. The user

populates the vector table during device initialization and updates it during operation.

1.5.4.1.1 Interrupt Operation Sequence

shows an overview of the interrupt operation sequence for all multiplexed PIE interrupts.

Interrupt sources that are not multiplexed are fed directly to the CPU.

(Enable/Flag)

SPRUH22I – April 2012 – Revised November 2019

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Figure 1-4. PIE Interrupts Multiplexing

PIEIERx(8:1)

Exceptions and Interrupts Control

PIEIFRx(8:1)

System Control and Interrupts

Peripherals or

Chapters

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