Adc Soc Overflow 1 Register (Adcsocovf1) (Address Offset 1Ch); Adc Soc Overflow Clear 1 Register (Adcsocovfclr1) (Address Offset 1Eh); Adc Soc Force 1 Register (Adcsocfrc1) Field Descriptions; Adc Soc Overflow 1 Register (Adcsocovf1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Analog-to-Digital Converter (ADC)
Table 10-18. ADC SOC Force 1 Register (ADCSOCFRC1) Field Descriptions
Bit Field
15-0 SOCx
(x = 15 to 0)
Figure 10-34. ADC SOC Overflow 1 Register (ADCSOCOVF1) (Address Offset 1Ch)
15 14
SOC15 SOC14
R-0 R-0
7 6
SOC7 SOC6
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-19. ADC SOC Overflow 1 Register (ADCSOCOVF1) Field Descriptions
Bit Field
15-0 SOCx
(x = 15 to 0)
Figure 10-35. ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) (Address Offset 1Eh)
15 14
SOC15 SOC14
R/W-0 R/W-0
7 6
SOC7 SOC6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-20. ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1) Field Descriptions
Bit Field
15-0 SOCx
(x = 15 to 0)
NOTE: The following ADC SOC0 - SOC15 Control Registers are EALLOW protected.
884
Analog Subsystem
Value Description
SOCx Force Start of Conversion Flag. Writing a 1 will force to 1 the respective SOCx flag bit in the
ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are
ignored.
0 No action.
1 Force SOCx flag bit to 1. This will cause a conversion to start once priority is given to SOCx.
If software tries to set this bit on the same clock cycle that hardware tries to clear the SOCx bit in
the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this
case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the
ADCSOCFLG1 bit was previously set or not.
13 12
SOC13 SOC12
R-0 R-0
5 4
SOC5 SOC4
R-0 R-0
Value Description
SOCx Start of Conversion Overflow Flag. Indicates an SOCx event was generated while an existing
SOCx event was already pending.
0 No SOCx event overflow
1 SOCx event overflow
An overflow condition does not stop SOCx events from being processed. It simply is an indication
that a trigger was missed
13 12
SOC13 SOC12
R/W-0 R/W-0
5 4
SOC5 SOC4
R/W-0 R/W-0
Value Description
SOCx Clear Start of Conversion Overflow Flag. Writing a 1 will clear the respective SOCx overflow
flag in the ADCSOCOVF1 register. Writes of 0 are ignored.
0 No action.
1 Clear SOCx overflow flag.
If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in
the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set.
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
SOC11 SOC10
R-0 R-0
3 2
SOC3 SOC2
R-0 R-0
11 10
SOC11 SOC10
R/W-0 R/W-0
3 2
SOC3 SOC2
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
9 8
SOC9 SOC8
R-0 R-0
1 0
SOC1 SOC0
R-0 R-0
9 8
SOC9 SOC8
R/W-0 R/W-0
1 0
SOC1 SOC0
R/W-0 R/W-0
Submit Documentation Feedback