Gpio Direction (Gpiodir) Register; Gpio Interrupt Sense (Gpiois) Register; Gpio Direction (Gpiodir) Register Field Descriptions; Gpio Interrupt Sense (Gpiois) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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4.1.6.2 GPIO Direction (GPIODIR) Register, offset 0x400
The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the
corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. All
bits are cleared by a reset, meaning all GPIO pins are inputs by default.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7-0 DIR
4.1.6.3 GPIO Interrupt Sense (GPIOIS) Register, offset 0x404
The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the
corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges.
All bits are cleared by a reset.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-8. GPIO Interrupt Sense (GPIOIS) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 IS
SPRUH22I – April 2012 – Revised November 2019
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Figure 4-5. GPIO Direction (GPIODIR) Register
R-0
Table 4-7. GPIO Direction (GPIODIR) Register Field Descriptions
Value Description
Reserved
GPIO Data Direction
0 Corresponding pin as an input.
1 Corresponding pin as an output.
Figure 4-6. GPIO Interrupt Sense (GPIOIS) Register
R-0
Value Description
Reserved
GPIO Interrupt Sense
0 The edge on the corresponding pin is detected (edge-sensitive).
1 The level on the corresponding pin is detected (level-sensitive).
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
Reserved
R-0
8 7
General-Purpose Input/Output (GPIO)
General-Purpose Input/Output (GPIO)
DIR
R/W-0
IS
R/W-0
16
0
16
0
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