Reset Control And Status Registers; Subsystem Reset Configuration/Control (Crescnf) Register; Control Subsystem Reset Status (Cressts) Register; Subsystem Reset Configuration/Control (Crescnf) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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System Control Registers

1.13.3 Reset Control and Status Registers

Figure 1-48. Subsystem Reset Configuration/Control (CRESCNF) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-59. Subsystem Reset Configuration/Control (CRESCNF) Register Field Descriptions

Figure 1-49. Control Subsystem Reset Status (CRESSTS) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-60. Control Subsystem Reset Status (CRESSTS) Register Field Descriptions

System Control and Interrupts

M3 Reset to ACIB

ACIBRESET to ACIB is low, causing a ACIB reset (holds Analog Subsystem in reset).

ACIBRESET to ACIB is high, enabling ACIB operation (allowing Analog Subsystem to run).

M3 Reset to C28 CPU

RSn to C28 CPU is low, causing a C28 CPU and C28 subsystem reset.

RSn to C28 CPU is high, bringing out the C28 CPU and subsystem out of reset.

C28 Reset Cause Flag – set by hardware when C28 HWBIST controller fired a reset to the C28

CPU; this flag does not indicate fail conditions – fail conditions cause an NMI to the M3 and C28

C28 CPU was not reset due to C28 HW BIST reset

C28 CPU was reset due to C28 HW BIST reset

This status bit is a latched flag This flag can be cleared by the M3 CPU by writing a "1"

Note: This flag is 2 bits to take care of any error conditions that may cause inadvertent setting of a

single bit flag;

SPRUH22I – April 2012 – Revised November 2019

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