Missing Clock Detection Logic - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Safety Features
1.6.1.3 Analog Subsystem Clocking Control Protection with Control System Lock Register (CLOCK)
As will be explained in the control subsystem clocking section, the ACIB and analog subsystem clocking
can be configured by setting the divider in the CCLKCTL register. The control subsystem can choose to
lock this clock configuration by setting the CCLKCTL bit (bit 1) in the CLOCK register. Once the control
subsystem locks this register, it cannot be re-written until the analog subsystem and ACIB are reset.
Please refer to Section 1.3
subsystem.

1.6.2 Missing Clock Detection Logic

A main oscillator verification circuit is provided that generates an error condition if the oscillator is running
too fast or too slow or goes missing. This logic is referred to as Missing Clock Detection logic.
The missing clock circuit detects if the clock is missing on the X1 pin. In the event of a missing clock
detection, the clock is automatically switched to the internal 10 MHz oscillator clock. This 10 MHz
oscillator will not be fed to the PLL. It is to be used only for error handling on clock missing condition
detection.
The following includes the missing clock detection scheme:
1. Missing clock detection circuitry is enabled by default so that a clock missing condition at power up can
be detected.
2. Missing clock detection can be disabled by a user programmable register.
3. At power up, on the rising edge of XRS, all counters related to the circuit are cleared (Described
below)
4. There is a 3-bit counter which runs off the 10 MHz clock. This counter will overflow approximately
every 800ns
5. There is also an 8-bit counter running with the OSCCLK source, which keeps updating a reference
clock count register.
6. There are two programmable registers which contain programmable limits for missing clock condition
detection: device reference clock count limit low, and clock count limit high registers. These registers
are programmable to allow support for the entire range of reference clock frequencies possible from 4
to 100 MHz. At reset, they are initialized to support the entire range of clock input frequencies. Refer to
the CLKLIMIT register description for reset values.
7. When the 3-bit 10 MHz clock counter overflows, it reads the OSCCLK reference clock count register
value (MCLKSTS.REFCLKCNT) and checks if the value falls between the limits defined in the clock
count limit registers
1. If yes,
a. then it means that the device input reference clock is still ticking within the defined frequency
range, enabling the counter to count properly as expected
b. since the reference clock is present, the OSCLK reference clock counter, count register
(MCLKSTS.REFCLKCNT), and 10 MHz clock counter are cleared and both the counters in the
circuit start counting again from 0.
2. If no,
a. the circuit will switch clocks to the 10 MHz internal oscillator clock - the system PLL is
bypassed and the 10 MHz clock becomes the clock source to the device.
b. since the reference clock is missing, the circuit generates a clock fail NMI to the M3 CPU and
C28 CPU, if enabled by the MCLKEN.MCLKNMIEN bit
c. the control subsystem PWM's, if enabled, are tripped automatically on clock fail.
8. On both the master and control subsystems, there is an NMI watch-dog, which is triggered when the
missing clock condition is detected.
9. If the M3 CPU does not respond to the NMI interrupt by the time the NMI WD expires, a reset will be
issued to the device.
10. On the control subsystem, upon receiving the missing clock NMI, the C28 CPU does the required
error handling and enters standby mode in the software ISR for the NMI. If the CNMIWD expires it will
generate a reset to the C28 CPU and C28 subsystem.
120
System Control and Interrupts
for more details on the resets that can reset the ACIB and the analog
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SPRUH22I – April 2012 – Revised November 2019
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