Adc Revision Register (Adcrev) (Address Offset 4Fh); Adc Result0 - Result15 Registers (Adcresultx) (Pf1 Block Address Offset 00H - 0Fh); Adc Offset Trim Register (Adcofftrim) Field Descriptions; Adc Revision Register (Adcrev) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Analog-to-Digital Converter (ADC)
Table 10-23. ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions
Bit Field
15-9 Reserved
8-0 OFFTRIM
10.3.11.7 ADC Revision Register
Figure 10-39. ADC Revision Register (ADCREV) (Address Offset 4Fh)
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-24. ADC Revision Register (ADCREV) Field Descriptions
Bit Field
15-8 REV
7-0 TYPE
10.3.11.8 ADC Result Registers
The ADC Result Registers are found in Peripheral Frame 0 (PF0). In the header files, the ADCRESULTx
registers are located in the AdcxResult register file, not AdcxRegs. The ADC Result Registers can also be
accessed by the M3 CPU.
Figure 10-40. ADC RESULT0 - RESULT15 Registers (ADCRESULTx) (PF1 Block Address Offset 00h
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-25. ADC RESULT0 - ADCRESULT15 Registers (ADCRESULTx) Field Descriptions
Bit Field
15-12 Reserved
11-0 RESULT
888
Analog Subsystem
Value Description
Reserved
ADC Offset Trim. 2's complement of ADC offset. Range is -256 to +255. These bits are loaded by
device boot code with a factory trim setting. Modification of this default setting can be made to
correct any board induced offset.
Value Description
ADC Revision. To allow documentation of differences between revisions. First version is labeled as
00h.
3 ADC Type. Always set to 3 for this type ADC
11
Value Description
Reserved
12-bit right-justified ADC result
Sequential Sampling Mode (SIMULENx = 0):
After the ADC completes a conversion of an SOCx, the digital result is placed in the corresponding
ADCRESULTx register. For example, if SOC4 is configured to sample ADCINA1, the completed
result of that conversion will be placed in ADCRESULT4.
Simultaneous Sampling Mode (SIMULENx = 1):
After the ADC completes a conversion of a channel pair, the digital results are found in the
corresponding ADCRESULTx and ADCRESULTx+1 registers (assuming x is even). For example,
for SOC4, the completed results of those conversions will be placed in ADCRESULT4 and
ADCRESULT5. See 1.11 for timings of when this register is written.
Copyright © 2012–2019, Texas Instruments Incorporated
REV
R-x
TYPE
R-3h
- 0Fh)
RESULT
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
0
0
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