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20.5.2.10 SSIDMACTL Register (Offset = 24h) [reset = 0h]
SSIDMACTL is shown in
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Summary
SSI DMA Control
31
30
23
22
15
14
7
6
Bit
Field
31-2
RESERVED
1
TXDMAE
0
RXDMAE
SPRUH22I – April 2012 – Revised November 2019
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Figure 20-19
and described in
Table.
Figure 20-19. SSIDMACTL Register
29
28
RESERVED
R-0h
21
20
RESERVED
R-0h
13
12
RESERVED
R-0h
5
4
RESERVED
R-0h
Table 20-13. SSIDMACTL Register Field Descriptions
Type
Reset
R
0h
R/W
0h
R/W
0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table
20-13.
27
26
19
18
11
10
3
2
Description
Reserved
Transmit DMA Enable
Value Description
0 uDMA for the transmit FIFO is disabled.
1 uDMA for the transmit FIFO is enabled.
Reset type: PER.RESET
Receive DMA Enable
Value Description
0 uDMA for the receive FIFO is disabled.
1 uDMA for the receive FIFO is enabled.
Reset type: PER.RESET
M3 Synchronous Serial Interface (SSI)
SSI Registers
25
24
17
16
9
8
1
0
TXDMAE
RXDMAE
R/W-0h
R/W-0h
1435
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