Sci Fifo Control (Sciffct) Register - Address 705Ch; Sci Fifo Control (Sciffct) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

SCI Registers
Table 13-16. SCI FIFO Receive (SCIFFRX) Register Field Descriptions (continued)
Bit Field
12-8 RXFFST4−0
7 RXFFINT
6 RXFFINT CLR
5 RXFFIENA
4-0 RXFFIL4−0
Figure 13-24. SCI FIFO Control (SCIFFCT) Register — Address 705Ch
15 14
ABD ABD CLR
R-0 W−0
7 6
FFTXDLY7 FFTXDLY6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-17. SCI FIFO Control (SCIFFCT) Register Field Descriptions
Bit Field
15 ABD
14 ABD CLR
13 CDC
12-8 Reserved
1004
C28 Serial Communications Interface (SCI)
Value Description
00000 Receive FIFO is empty
00001 Receive FIFO has 1 word
00010 Receive FIFO has 2 words
00011 Receive FIFO has 3 words
0xxxx Receive FIFO has x words
10000 Receive FIFO has 16 words
Receive FIFO interrupt
0 RXFIFO interrupt has not occurred, read-only bit
1 RXFIFO interrupt has occurred, read-only bit
Receive FIFO interrupt clear
0 Write 0 has no effect on RXFIFINT flag bit. Bit reads back a zero.
1 Write 1 to clear RXFFINT flag in bit 7
Receive FIFO interrupt enable
0 RX FIFO interrupt based on RXFFIL match (greater than or equal to) is disabled
1 RX FIFO interrupt based on RXFFIL match (less than or equal to) will be enabled.
Receive FIFO interrupt level bits
11111 The receive FIFO generates an interrupt whenever the FIFO status bits (RXFFST4-0) are greater
than or equal to the FIFO level bits (RXFFIL4-0). The maximum value that can be assigned to
these bits to generate an interrupt cannot be more than the depth of the RX FIFO. The default
value of these bits after reset is 11111b. Users should set RXFFIL to best fit their application needs
by weighing between the CPU overhead to service the ISR and the best possible usage of received
SCI data.
13 12
CDC
R/W−0
5 4
FFTXDLY5 FFTXDLY4
R/W-0 R/W-0
Value Description
Auto-baud detect (ABD) bit.
0 Auto-baud detection is not complete. "A","a" character has not been received successfully.
1 Auto-baud hardware has detected "A" or "a" character on the SCI receive register. Auto-detect is
complete.
ABD-clear bit
0 Write 0 has no effect on ABD flag bit. Bit reads back a zero.
1 Write 1 to clear ABD flag in bit 15.
CDC calibrate A-detect bit
0 Disables auto-baud alignment
1 Enables auto-baud alignment
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
FFTXDLY3 FFTXDLY2
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
1 0
FFTXDLY1 FFTXDLY0
R/W-0 R/W-0
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