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17.11.25 EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308
NOTE: The MODE field in the EPICFG register configures whether EPI Host Bus mode is enabled.
For EPIHB8CFG3 to be valid, the MODE field must be 0x2.
Figure 17-52. EPI Host-Bus 8 Configuration 3 Register (EPIHB8CFG3) [offset 0x308]
31
Reserved
R-0
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-38. EPI Host-Bus 8 Configuration 3 Register (EPIHB8CFG3) Field Descriptions
Bit
Field
31-22
Reserved
21
WRHIGH
20
RDHIGH
19
ALEHIGH
18-8
Reserved
7-6
WRWS
5-4
RDWS
3-2
Reserved
SPRUH22I – April 2012 – Revised November 2019
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22
R-0
Value
Description
0
Reserved
CS2 WRITE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2 .
0
The WRITE strobe for CS2 accesses is WR (active Low).
1
The WRITE strobe for CS2 accesses is WR (active High).
CS2 READ Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
0
The READ strobe for CS2 accesses is RD (active Low).
1
The READ strobe for CS2 accesses is RD (active High).
CS2 ALE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
0
The address latch strobe for CS2 accesses is ADV (active Low).
1
The address latch strobe for CS2 accesses is ALE (active High).
Reserved
CS2 Write Wait States
This field is used in conjunction with the EPIBAUD register.
This field adds wait states to the data phase of CS2 accesses (the address phase is not affected).
The effect is to delay the rising edge of WR (or the falling edge of WR). Each wait state adds two
EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME3 register can decrease
the number of wait states by one EPI clock cycle for greater granularity. This field is used if the
CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode.
0x0
Active WRn is 2 EPI clocks
0x1
Active WR is 4 EPI clocks
0x2
Active WR is 6 EPI clocks
0x3
Active WR is 8 EPI clocks
CS2 Read Wait States
This field is used in conjunction with the EPIBAUD register.
This field adds wait states to the data phase of CS2 accesses (the address phase is not affected).
The effect is to delay the rising edge of RD/Oe (or the falling edge of RD). Each wait state adds 2
EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME3 register can decrease
the number of wait states by 1 EPI clock cycle for greater granularity. This field is used if the
CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode.
0x0
Active RD is 2 EPI clocks
0x1
Active RD is 4 EPI clocks
0x2
Active RD is 6 EPI clocks
0x3
Active RD is 8 EPI clocks
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
21
20
WRHIGH
RDHIGH
R/W-0
R/W-0
8
7
6
5
WRWS
RDWS
R/W-0
R/W-0
Register Descriptions
19
18
ALEHIGH
Reserved
R/W-1
R-0
4
3
2
1
Reserved
MODE
R-0
R/W-0
External Peripheral Interface (EPI)
16
0
1263
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