Digital-Compare Submodule High-Level Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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7.2.9 Digital Compare (DC) Submodule
Figure 7-47 illustrates where the digital compare (DC) submodule signals interface to other submodules in
the ePWM system.
Figure 7-47. Digital-Compare Submodule High-Level Block Diagram
GPIO
GPTRIP
MUX
The ECAP input signals are sourced from the GPTRIP signals as shown in
SPRUH22I – April 2012 – Revised November 2019
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TRIPIN1 and TZ1
TRIPIN2 and TZ2
TRIPIN10
TRIPIN11
TRIPIN12
TRIPIN14 [ECCDBLERR]
TRIPIN15 [PIEERR]
TRIPIN1 and TZ1
TRIPIN2 and TZ2
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
TRIPIN14 [ECCDBLERR]
TRIPIN15 [PIEERR]
[DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL]
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Digital Compare Submodule
DCAH DCAEVT1
Event A
DCAL DCAEVT2
Qual
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
DCBH DCBEVT1
Event B
DCBL DCBEVT2
Qual
C28 Enhanced Pulse Width Modulator (ePWM) Module
ePWM Submodules
DCAEVT1.sync
DCBEVT1.sync
DCAEVT1.force
DCAEVT2.force
Event
Filtering
DCBEVT1.force
DCBEVT2.force
DCEVTFILT
Blanking Event
DCAEVT1.inter
Window Triggering
DCAEVT2.inter
Counter
DCBEVT1.inter
Capture
DCBEVT2.inter
DCAEVT1.soc
DCBEVT1.soc
Figure 7-48.
Time-Base
submodule
Trip-Zone
submodule
Event-Trigger
submodule
699