Gpio Port E Pullup Disable (Gpepud); Analog I/O Dir (Aiodir) Register; Gpio Port E Pullup Disable (Gpepud) Register Field Descriptions; Analog I/O Dir (Aiodir) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

C28 General-Purpose Input/Output (GPIO)
4.2.7.23 GPIO Port E Pullup Disable (GPEPUD) Register
The GPIO Port E Pullup Disable (GPEPUD) register is shown and described in the figure and table below.
31
15
7 6
GPIO135 GPIO134
R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-72. GPIO Port E Pullup Disable (GPEPUD) Register Field Descriptions
Bits Field
31-8 Reserved
7-0 GPIO135-GPIO128
(1)
All other pins' pullup functionality is controlled by the GPIOPUR register located in the M3 GPIO mux register rspace.

4.2.7.24 Analog I/O DIR (AIODIR) Register

The Analog I/O DIR (AIODIR) register is shown and described in the figure and table below.
31 30
Reserved AIO30
R-0 R/W-x
23 22
Reserved AIO22
R-0 R/W-x
15 14
Reserved AIO14
R-0 R/W-x
7 6
Reserved AIO6
R-0 R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after resetR/W-x
Bit Field
31:0 AIOn
412
General-Purpose Input/Output (GPIO)
Figure 4-64. GPIO Port E Pullup Disable (GPEPUD)
5 4
GPIO133 GPIO132
R/W-1 R/W-1
Value
Any writes to these bit(s) must always have a value of 0.
Configures the internal pullup resistor on the selected GPIO Port E pin. Each GPIO pin
corresponds to one bit in this register.
0 Enable the internal pullup on the specified pin.
1 Disable the intenral pullup on the specified pin (default).
Figure 4-65. Analog I/O DIR (AIODIR) Register
29 28
Reserved AIO28
R-0 R/W-x
21 20
Reserved AIO20
R-0 R/W-x
13 12
Reserved AIO12
R-0 R/W-x
5 4
Reserved AIO4
R-0 R/W-x
Table 4-73. Analog I/O DIR (AIODIR) Register Field Descriptions
Value Description
Controls direction of the avaliable AIO pin when AIO mode is selected. Reading the register returns
the current value of the register setting.
0 Configures the AIO pin as an input. (default)
1 Configures the AIO pin as an output
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R/W-0
Reserved
R/W-0xF
3 2
GPIO131 GPIO130
R/W-1 R/W-1
Description
27 26
Reserved AIO26
R-0 R/W-x
19 18
Reserved AIO18
R-0 R/W-x
11 10
Reserved AIO10
R-0 R/W-x
3 2
Reserved AIO2
R-0 R/W-x
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
1
GPIO129 GPIO128
R/W-1 R/W-1
(1)
25
Reserved
R-0
17
Reserved
R-0
9
Reserved
R-0
1
Reserved
R-0
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16
8
0
24
16
8
0