Transmit Channel Enable Registers (Xcera, Xcerb, Xcerc, Xcerd, Xcere, Xcerf, Xcerg, Xcerh); Transmit Channel Enable Registers (Xcera - Texas Instruments Concerto F28M35 Series Technical Reference Manual

McBSP Registers
Table 15-89. Use of the Receive Channel Enable Registers (continued)
Number of
Selectable
Channels
15.12.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE,
XCERF, XCERG, XCERH)
Each McBSP has eight transmit channel enable registers of the form shown in
for each of the transmit partitions: A, B, C, D, E, F, G, and H.
that applies to each bit XCEx of a transmit channel enable register.
The XCERs are only used when the transmitter is configured to allow individual disabling/enabling and
masking/unmasking of the channels (XMCM is nonzero).
The transmit channel enable registers (XCERA...XCERH) are shown in
Table 15-90.
Figure 15-79. Transmit Channel Enable Registers (XCERA...XCERH)
15 14
XCE15 XCE14
R/W-0 R/W-0
7 6
XCE7 XCE6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-90. Transmit Channel Enable Registers (XCERA...XCERH) Field Descriptions
Bit Field
15-0 XCEx
1142
C28 Multichannel Buffered Serial Port (McBSP)
Block Assignments
RCERx Block Assigned
RCERH Block 7
13 12
XCE13 XCE12
R/W-0 R/W-0
5 4
XCE5 XCE4
R/W-0 R/W-0
Value Description
Transmit channel enable bit. The role of this bit depends on which transmit multichannel selection
mode is selected with the XMCM bits.
For multichannel selection when XMCM = 01b
(all channels disabled unless selected):
0 Disable and mask the channel that is mapped to XCEx.
1 Enable and unmask the channel that is mapped to XCEx.
For multichannel selection when XMCM = 10b
(all channels enabled but masked unless selected):
0 Mask the channel that is mapped to XCEx.
1 Unmask the channel that is mapped to XCEx.
For multichannel selection when XMCM = 11b
(all channels masked unless selected):
0 Mask the channel that is mapped to XCEx. Even if the channel is enabled by the corresponding
receive channel enable bit, this channel's data cannot appear on the DX pin.
1 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding
receive channel enable bit, full transmission can occur.
Copyright © 2012–2019, Texas Instruments Incorporated
Channel Assignments
Bit in RCERx
RCE0
RCE1
RCE2
:
RCE15
Figure
Table 15-90 provides a summary description
Figure 15-79
11 10
XCE11 XCE10
R/W-0 R/W-0
3 2
XCE3 XCE2
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Channel Assigned
Channel 112
Channel 113
Channel 114
:
Channel 127
15-79. There is one
and described in
9 8
XCE9 XCE8
R/W-0 R/W-0
1 0
XCE1 XCE0
R/W-0 R/W-0
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