Adc Interrupt Flag Clear Register (Adcintflgclr) (Address Offset 05H); Adc Interrupt Overflow Register (Adcintovf) (Address Offset 06H); Adc Interrupt Overflow Clear Register (Adcintovfclr) (Address Offset 07H); Adc Interrupt Flag Clear Register (Adcintflgclr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Analog-to-Digital Converter (ADC)
Figure 10-20. ADC Interrupt Flag Clear Register (ADCINTFLGCLR) (Address Offset 05h)
15
7 6
ADCINT8 ADCINT7
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-9. ADC Interrupt Flag Clear Register (ADCINTFLGCLR) Field Descriptions
Bit Field
15-8 Reserved
7-0 ADCINTx
(x = 8 to 1)
Figure 10-21. ADC Interrupt Overflow Register (ADCINTOVF) (Address Offset 06h)
15
7 6
ADCINT8 ADCINT7
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-10. ADC Interrupt Overflow Register (ADCINTOVF) Field Descriptions
Bit Field
15-8 Reserved
7-0 ADCINTx
(x = 8 to 1)
Figure 10-22. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) (Address Offset 07h)
15
7 6
ADCINT8 ADCINT7
R-0/W-1 R-0/W-1
LEGEND: R/W = Read/Write; R = Read only; R-0/W-1 =always read 0, write 1 to set; -n = value after reset
876
Analog Subsystem
5 4
ADCINT6 ADCINT5
R/W-0 R/W-0
Value Description
0 Reserved
ADC interrupt Flag Clear Bit
0 No action.
1 Clears respective flag bit in the ADCINTFLG register. If software tries to set this bit on the same
clock cycle that hardware tries to set the flag bit in the ADCINTFLG register, then hardware has
priority and the ADCINTFLG bit will be set. In this case the overflow bit in the ADCINTOVF register
will not be affected regardless of whether the ADCINTFLG bit was previously set or not.
5 4
ADCINT6 ADCINT5
R-0 R-0
Value Description
0 Reserved
ADC Interrupt Overflow Bits.
Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit
is set and a selected additional EOC trigger is generated, then an overflow condition occurs.
0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.
The overflow bit does not care about the continuous mode bit state. An overflow condition is
generated irrespective of this mode selection.
5 4
ADCINT6 ADCINT5
R-0/W-1 R-0/W-1
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
ADCINT4 ADCINT3
R/W-0 R/W-0
Reserved
R-0
3 2
ADCINT4 ADCINT3
R-0 R-0
Reserved
R-0
3 2
ADCINT4 ADCINT3
R-0/W-1 R-0/W-1
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
9 8
1 0
ADCINT2 ADCINT1
R/W-0 R/W-0
9 8
1 0
ADCINT2 ADCINT1
R-0 R-0
9 8
1 0
ADCINT2 ADCINT1
R-0/W-1 R-0/W-1
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