Range Of Programmable Data Delay - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Receiver Configuration
Table 15-31. Register Bits Used to Set the Receive Data Delay (continued)
Register Bit
15.8.12.1 Data Delay
The start of a frame is defined by the first clock cycle in which frame synchronization is found to be active.
The beginning of actual data reception or transmission with respect to the start of the frame can be
delayed if required. This delay is called data delay.
RDATDLY specifies the data delay for reception. The range of programmable data delay is zero to two bit-
clocks (RDATDLY = 00b-10b), as described in
data transferred is an 8-bit value with bits labeled B7, B6, B5, and so on. Typically a 1-bit delay is
selected, because data often follows a 1-cycle active frame-synchronization pulse.
15.8.12.2 0-Bit Data Delay
Normally, a frame-synchronization pulse is detected or sampled with respect to an edge of internal serial
clock CLK(R/X). Thus, on the following cycle or later (depending on the data delay value), data may be
received or transmitted. However, in the case of 0-bit data delay, the data must be ready for reception
and/or transmission on the same serial clock cycle.
For reception, this problem is solved because receive data is sampled on the first falling edge of MCLKR
where an active-high internal FSR is detected. However, data transmission must begin on the rising edge
of the internal CLKX clock that generated the frame synchronization. Therefore, the first data bit is
assumed to be present in XSR1, and thus on DX. The transmitter then asynchronously detects the frame-
synchronization signal (FSX) going active high and immediately starts driving the first bit to be transmitted
on the DX pin.
CLK(R/X)
FS(R/X)
D(R/X)
Data delay 0
D(R/X)
Data delay 1
D(R/X)
Data delay 2
15.8.12.3 2-Bit Data Delay
A data delay of two bit periods allows the serial port to interface to different types of T1 framing devices
where the data stream is preceded by a framing bit. During reception of such a stream with data delay of
two bits (framing bit appears after a 1-bit delay and data appears after a 2-bit delay), the serial port
essentially discards the framing bit from the data stream, as shown in
transferred is an 8-bit value with bits labeled B7, B6, B5, and so on.
1086
C28 Multichannel Buffered Serial Port (McBSP)
Name Function
RDATDLY = 11
Figure 15-46. Range of Programmable Data Delay
0-bit delay
B7
1-bit delay
2-bit delay
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Table 15-31 and shown in
B6 B5
B7 B6
B7
Figure
SPRUH22I – April 2012 – Revised November 2019
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Type
Figure 15-46. In this figure, the
B4 B3
B5 B4
B6 B5
15-47. In this figure, the data
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