Can Bit Timing; Cpu Handling Of A Fifo Buffer (Interrupt Driven) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com
NOTE: All message objects of a FIFO buffer needs to be read and cleared before the next batch of
messages can be stored. Otherwise true FIFO functionality cannot be guaranteed, since the
message objects of a partly read buffer will be re-filled according to the normal (descending)
priority.
Reading from a FIFO Buffer message object and resetting its NewDat bit is handled the same way as
reading from a single message object.
Figure 23-10. CPU Handling of a FIFO Buffer (Interrupt Driven)

23.12 CAN Bit Timing

The CAN supports bit rates between 1 kBit/s and 1000 kBit/s.
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
START
Read interrupt identifier
case interrupt identifier
0x800
Status Change
Interrupt Handling
IFx command register [31:16] = 0x007F
Message Number = interrupt identifier
Write Message Number to IF1/IF2 command register
(Transfer message to IF1/IF2 registers,
clear NewDat and IntPnd)
Read IF1/IF2 message control
NewDat = 1
Read data from IF1/IF2 Data A,B
EoB = 1
Next Message Number in this FIFO Buffer
Copyright © 2012–2019, Texas Instruments Incorporated
Message interrupt
else 0x0000
END
No
Yes
Yes
No
M3 Controller Area Network (CAN)
CAN Bit Timing
1529