Can Control Register (Can Ctl); Can Control Register (Can Ctl) [Offset = 0X00] - Texas Instruments Concerto F28M35 Series Technical Reference Manual

CAN Control Registers
Offset
0x14
0x1C
0x80
0x88
0x9C
0xB0
0xC4
0xD8
0x100
0x104
0x108
0x10C
0x110
0x114
0x120
0x124
0x128
0x12C
0x130
0x134
0x140
0x144
0x148
0x14C
0x150
0x154
0x160
After hardware reset, the registers of the CAN hold the values shown in the register descriptions.
Additionally, the bus-off state is reset and the CAN_TX pin is set to recessive (HIGH). The Init bit in the
CAN Control register is set to enable the software initialization. The CAN will not influence the CAN bus
until the CPU resets Init to '0'.

23.15.1 CAN Control Register (CAN CTL)

The CAN Control register (CAN CTL) is shown and described in the figure and table below.
31
Reserved
R-0
15 14 13
SWR Rsvd
R/WP- R-0 R/W-0x5
0
LEGEND: R = Read; R/W = Read/Write; WP = Write Protected by Init bit; -n = value after reset
1544
M3 Controller Area Network (CAN)
Table 23-4. CAN Control Registers (continued)
Acronym Register Description
CAN TEST Test Register
CAN PERR Parity Error Code Register
CAN ABOTR Auto-Bus-On Time Register
CAN TXRQ Transmission Request Register
CAN NWDAT New Data Register
CAN INTPND Interrupt Pending Register
CAN MSGVAL Message Valid Register
CAN INTMUX Interrupt Multiplexer Register
CAN IF1CMD IF1 Command Register
CAN IF1MSK IF1 Mask Register
CAN IF1ARB IF1 Arbitration Register
CAN IF1MCTL IF1 Message Control Register
CAN IF1DATA IF1 Data A Register
CAN IF1DATB IF1 Data B Register
CAN IF2CMD IF2 Command Register
CAN IF2MSK IF2 Mask Register
CAN IF2ARB IF2 Arbitration Register
CAN IF2MCTL IF2 Message Control Register
CAN IF2DATA IF2 Data A Register
CAN IF2DATB IF2 Data B Register
CAN IF3OBS IF3 Observation Register
CAN IF3MSK IF3 Mask Register
CAN IF3ARB IF3 Arbitration Register
CAN IF3MCTL IF3 Message Control Register
CAN IF3DATA IF3 Data A Register
CAN IF3DATB IF3 Data B Register
CAN IF3UPD IF3 Update Enable Register
Figure 23-19. CAN Control Register (CAN CTL) [offset = 0x00]
26 25
WUBA PDR
R/W-0 R/W-0
10 9
PMD ABO
R/W-0 R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
24 23
Reserved
R-0
8 7 6 5
IDS Test CCE DAR
R/W-0 R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
See
Section 23.15.6
Section 23.15.7
Section 23.15.8
Section 23.15.9
Section 23.15.10
Section 23.15.11
Section 23.15.12
Section 23.15.13
Section 23.15.14
Section 23.15.15
Section 23.15.16
Section 23.15.17
Section 23.15.18
Section 23.15.18
Section 23.15.14
Section 23.15.15
Section 23.15.16
Section 23.15.17
Section 23.15.18
Section 23.15.18
Section 23.15.19
Section 23.15.20
Section 23.15.21
Section 23.15.22
Section 23.15.23
Section 23.15.23
Section 23.15.24
18 17
IE1
R/W-0
4 3 2 1
Rsvd EIE SIE IE0
R-0 R/W-0 R/W-0 R/W-0
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16
InitDbg
R-0
0
Init
R/W-1