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To enable DMA operation for the endpoint receive channel, the DMAEN bit of the USBRXCSRHn register
should be set. To enable DMA operation for the endpoint transmit channel, the DMAEN bit of the
USBTXCSRHn register must be set.
See the Micro Direct Memory Access (μDMA) chapter for more details about programming the μDMA
controller.
18.3 Initialization and Configuration
To use the USB Controller, the peripheral clock must be enabled via the RCGC2 register (see the System
Control chapter). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register in the System Control module. Configure the PMCn fields in the GPIOPCTL register to assign the
USB signals to the appropriate pins (see the GPIOs chapter).
The initial configuration in all cases requires that the processor enable the USB controller and USB
controller's physical layer interface (PHY) before setting any registers. The next step is to enable the USB
PLL so that the correct clocking is provided to the PHY. To ensure that voltage is not supplied to the bus
incorrectly, the external power control signal, USB0EPEN, should be negated on start up by configuring
the USB0EPEN and USB0PFLT pins to be controlled by the USB controller and not exhibit their default
GPIO behavior.
Note: When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they are
dedicated pins for the USB controller and directly connect to the USB connector's VBUS and ID signals. If
the USB controller is used as either a dedicated Host or Device, the DEVMODOTG and DEVMOD bits in
the USB General-Purpose Control and Status (USBGPCS) register can be used to connect the
USB0VBUS and USB0ID inputs to fixed levels internally, freeing the pins for GPIO use. For proper self-
powered Device operation, the VBUS value must still be monitored to assure that if the Host removes
VBUS, the self-powered Device disables the D+/D- pull-up resistors. This function can be accomplished
by connecting a standard GPIO to VBUS.
18.3.1 Pin Configuration
When using the device controller portion of the USB controller in a system that also provides Host
functionality, the power to VBUS must be disabled to allow the external Host controller to supply power.
Usually, the USB0EPEN signal is used to control the external regulator and should be negated to avoid
having two devices driving the USB0VBUS power pin on the USB connector.
When the USB controller is acting as a Host, it is in control of two signals that are attached to an external
voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal to enable or
disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT, provides feedback
when there has been a power fault on VBUS. The USB0PFLT signal can be configured to either
automatically negate the USB0EPEN signal to disable power, and/or it can generate an interrupt to the
interrupt controller to allow software to handle the power fault condition. The polarity and actions related to
both USB0EPEN and USB0PFLT are fully configurable in the USB controller. The controller also provides
interrupts on device insertion and removal to allow the Host controller code to respond to these external
events.
18.3.2 Endpoint Configuration
To start communication in Host or device mode, the endpoint registers must first be configured. In Host
mode, this configuration establishes a connection between an endpoint register and an endpoint on a
device. In device mode, an endpoint must be configured before enumerating to the Host controller.
In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a software-based
state machine to progress through the setup, data, and status phases of a standard control transaction. In
device mode, the configuration of the remaining endpoints is done once before enumerating and then only
changed if an alternate configuration is selected by the Host controller. In Host mode, the endpoints must
be configured to operate as control, bulk, interrupt or isochronous mode. Once the type of endpoint is
configured, a FIFO area must be assigned to each endpoint. In the case of bulk, control and interrupt
endpoints, each has a maximum of 64 bytes per transaction. Isochronous endpoints can have packets
with up to 1023 bytes per packet. In either mode, the maximum packet size for the given endpoint must be
set prior to sending or receiving data.
SPRUH22I – April 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
Initialization and Configuration
M3 Universal Serial Bus (USB) Controller
1291
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