Adc Sample Mode Register (Adcsamplemode) (Address Offset 12H); Adc Sample Mode Register (Adcsamplemode) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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10.3.11.5 ADC SOC Registers
NOTE: The following ADC Sample Mode Register is EALLOW protected.
Figure 10-29. ADC Sample Mode Register (ADCSAMPLEMODE) (Address Offset 12h)
15
7 6
SIMULEN14 SIMULEN12
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-14. ADC Sample Mode Register (ADCSAMPLEMODE) Field Descriptions
Bit Field
15:8 Reserved
7 SIMULEN14
6 SIMULEN12
5 SIMULEN10
4 SIMULEN8
SPRUH22I – April 2012 – Revised November 2019
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5 4
SIMULEN10 SIMULEN8
R/W-0 R/W-0
Value Description
0 Reserved
Simultaneous sampling enable for SOC14/SOC15. Couples SOC14 and SOC15 in simultaneous
sampling mode. See Section 10.3.6
converting SOC14 or SOC15.
0 Single sample mode set for SOC14 and SOC15. All bits of CHSEL field define channel to be
converted. EOC14 associated with SOC14. EOC15 associated with SOC15. SOC14's result placed
in ADCRESULT14 register. SOC15's result placed in ADCRESULT15.
1 Simultaneous sample for SOC14 and SOC15. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC14 and EOC15 associated with SOC14 and SOC15 pair. SOC14's
and SOC15's results will be placed in ADCRESULT14 and ADCRESULT15 registers, respectively.
Simultaneous sampling enable for SOC12/SOC13. Couples SOC12 and SOC13 in simultaneous
sampling mode. See Section 10.3.6
converting SOC12 or SOC13.
0 Single sample mode set for SOC12 and SOC13. All bits of CHSEL field define channel to be
converted. EOC12 associated with SOC12. EOC13 associated with SOC13. SOC12's result placed
in ADCRESULT12 register. SOC13's result placed in ADCRESULT13.
1 Simultaneous sample for SOC12 and SOC13. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC12 and EOC13 associated with SOC12 and SOC13 pair. SOC12's
and SOC13's results will be placed in ADCRESULT12 and ADCRESULT13 registers, respectively.
Simultaneous sampling enable for SOC10/SOC11. Couples SOC10 and SOC11 in simultaneous
sampling mode. See Section 10.3.6
converting SOC10 or SOC11.
0 Single sample mode set for SOC10 and SOC11. All bits of CHSEL field define channel to be
converted. EOC10 associated with SOC10. EOC11 associated with SOC11. SOC10's result placed
in ADCRESULT10 register. SOC11's result placed in ADCRESULT11.
1 Simultaneous sample for SOC10 and SOC11. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC10 and EOC11 associated with SOC10 and SOC11 pair. SOC10's
and SOC11's results will be placed in ADCRESULT10 and ADCRESULT11 registers, respectively.
Simultaneous sampling enable for SOC8/SOC9. Couples SOC8 and SOC9 in simultaneous
sampling mode. See Section 10.3.6
converting SOC8 or SOC9.
0 Single sample mode set for SOC8 and SOC9. All bits of CHSEL field define channel to be
converted. EOC8 associated with SOC8. EOC9 associated with SOC9. SOC8's result placed in
ADCRESULT8 register. SOC9's result placed in ADCRESULT9.
1 Simultaneous sample for SOC8 and SOC9. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC8 and EOC9 associated with SOC8 and SOC9 pair. SOC8's and
SOC9's results will be placed in ADCRESULT8 and ADCRESULT9 registers, respectively.
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R-0
3 2
SIMULEN6 SIMULEN4
R/W-0 R/W-0
for details. This bit should not be set when the ADC is actively
for details. This bit should not be set when the ADC is actively
for details. This bit should not be set when the ADC is actively
for details. . This bit should not be set when the ADC is actively
Analog-to-Digital Converter (ADC)
8
1 0
SIMULEN2 SIMULEN0
R/W-0 R/W-0
Analog Subsystem
881