Debug Interrupt Enable Register (Dbgier); Debug Interrupt Enable Register (Dbgier) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 1-86. CPU Interrupt Enable Register (IER) Field Descriptions (continued)
Bits Field
5 INT6
4 INT5
3 INT4
2 INT3
1 INT2
0 INT1

1.13.5.13.7 Debug Interrupt Enable Register (DBGIER)

The Debug Interrupt Enable Register (DBGIER) is used only when the CPU is halted in real-time
emulation mode. An interrupt enabled in the DBGIER is defined as a time-critical interrupt. When the CPU
is halted in real-time mode, the only interrupts that are serviced are time-critical interrupts that are also
enabled in the IER. If the CPU is running in real-time emulation mode, the standard interrupt-handling
process is used and the DBGIER is ignored.
As with the IER, you can read the DBGIER to identify enabled or disabled interrupts and write to the
DBGIER to enable or disable interrupts. To enable an interrupt, set its corresponding bit to 1. To disable
an interrupt, set its corresponding bit to 0. Use the PUSH DBGIER instruction to read from the DBGIER
and POP DBGIER to write to the DBGIER register. At reset, all the DBGIER bits are set to 0.
15 14
RTOSINT DLOGINT
R/W-0 R/W-0
7 6
INT8 INT7
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-87. Debug Interrupt Enable Register (DBGIER) Field Descriptions
Bits Field
15 RTOSINT
14 DLOGINT
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Interrupt 6 enable. INT6 enables or disables CPU interrupt level INT6.
0 Level INT6 is disabled
1 Level INT6 is enabled
Interrupt 5 enable.INT5 enables or disables CPU interrupt level INT5.
0 Level INT5 is disabled
1 Level INT5 is enabled
Interrupt 4 enable.INT4 enables or disables CPU interrupt level INT4.
0 Level INT4 is disabled
1 Level INT4 is enabled
Interrupt 3 enable.INT3 enables or disables CPU interrupt level INT3.
0 Level INT3 is disabled
1 Level INT3 is enabled
Interrupt 2 enable.INT2 enables or disables CPU interrupt level INT2.
0 Level INT2 is disabled
1 Level INT2 is enabled
Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1.
0 Level INT1 is disabled
1 Level INT1 is enabled
Figure 1-76. Debug Interrupt Enable Register (DBGIER)
13 12
INT14 INT13
R/W-0 R/W-0
5 4
INT6 INT5
R/W-0 R/W-0
Value Description
Real-time operating system interrupt enable. RTOSINT enables or disables the CPU RTOS
interrupt.
0 Level INT6 is disabled
1 Level INT6 is enabled
. Data logging interrupt enable. DLOGINT enables or disables the CPU data logging interrupt
0 Level INT6 is disabled
1 Level INT6 is enabled
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11 10
INT12 INT11
R/W-0 R/W-0
3 2
INT4 INT3
R/W-0 R/W-0
System Control and Interrupts
System Control Registers
9 8
INT10 INT9
R/W-0 R/W-0
1 0
INT2 INT1
R/W-0 R/W-0
213