If1 And If2 Data A And Data B Registers (Can If1Data/Datb, Can If2Data/Datb); If1 Data A Register (Can If1Data) [Offset = 0X110]; If1 Data B Register (Can If1Datb) [Offset = 0X114]; If2 Data A Register (Can If2Data) [Offset = 0X130] - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 23-21. IF1 and IF2 Message Control Registers Field Descriptions (continued)
Bit Field
8 TxRqst
7 EoB
6-5 Reserved
3-0 DLC[3:0]
23.15.18

IF1 and IF2 Data A and Data B Registers (CAN IF1DATA/DATB, CAN IF2DATA/DATB)

The data bytes of CAN messages are stored in the IF1 and IF2 registers in the following order. In a CAN
data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit
stream, the MSB of each byte will be transmitted first
31
15
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset
31
15
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset
31
15
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Transmit Request
0 This message object is not waiting for a transmission.
1 The transmission of this message object is requested and is not yet done.
End of Block
0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO
Buffer block.
1 The message object is a single message object or the last message object in a FIFO Buffer Block.
Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single
message objects (not belonging to a FIFO Buffer), this bit must always be set to one.
Reserved
Data length code
0-8 Data frame has 0-8 data bits.
9-15 data frame has 8 data bytes.
Note: The data length code of a message object must be defined the same as in all the
corresponding objects with the same identifier at other nodes. When the message handler stores a
data frame, it will write the DLC to the value given by the received message.
Figure 23-40. IF1 Data A Register (CAN IF1DATA) [offset = 0x110]
Data 3
R/WP-0
Data 1
R/WP-0
Figure 23-41. IF1 Data B Register (CAN IF1DATB) [offset = 0x114]
Data 7
R/WP-0
Data 5
R/WP-0
Figure 23-42. IF2 Data A Register (CAN IF2DATA) [offset = 0x130]
Data 3
R/WP-0
Data 1
R/WP-0
Copyright © 2012–2019, Texas Instruments Incorporated
24 23
8 7
24 23
8 7
24 23
8 7
CAN Control Registers
Data 2
R/WP-0
Data 0
R/WP-0
Data 6
R/WP-0
Data 4
R/WP-0
Data 2
R/WP-0
Data 0
R/WP-0
M3 Controller Area Network (CAN)
16
0
16
0
16
0
1561