Introduction; Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Introduction

21.1 Introduction

The Universal Asynchronous Receiver/Transmitter (UART) includes the following features:

Programmable baud-rate generator allowing speeds up to M3 System clock / 16 for regular speed and

M3 System clock / 8 for high speed

Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered

FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

Standard asynchronous communication bits for start, stop, and parity

Line-break generation and detection

Fully programmable serial interface characteristics

– 5, 6, 7, or 8 data bits

– Even, odd, stick, or no-parity bit generation/detection

– 1 or 2 stop bit generation

IrDA serial-IR (SIR) encoder/decoder providing

– Programmable use of IrDA Serial Infrared (SIR) or UART input/output

– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex

– Support of normal 3/16 and low-power (1.41-2.23 µs) bit durations

– Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-

power mode bit duration

Support for communication with ISO 7816 smart cards

LIN protocol support

Standard FIFO-level and End-of-Transmission interrupts

Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted at programmed

– Transmit single request asserted when there is space in the FIFO; burst request asserted at

programmed FIFO level

shows the UART block diagram.

M3 Universal Asynchronous Receivers/Transmitters (UARTs)

SPRUH22I – April 2012 – Revised November 2019

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