Multiplexed Interrupt Request Flow - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Exceptions and Interrupts Control
3. Modify the PIE vector table to temporarily map the vector of the specific peripheral interrupt to a empty
interrupt service routine (ISR). This empty ISR will only perform a return from interrupt (IRET)
instruction. This is the safe way to clear a single PIEIFRx.y bit without losing any interrupts from other
peripherals within the group.
4. Disable the peripheral interrupt at the peripheral register.
5. Enable global interrupts (INTM = 0).
6. Wait for any pending interrupt from the peripheral to be serviced by the empty ISR routine.
7. Disable global interrupts (INTM = 1).
8. Modify the PIE vector table to map the peripheral vector back to its original ISR.
9. Clear the EALLOW bit.
10. Disable the PIEIER bit for given peripheral.
11. Clear the IFR bit for given peripheral group (this is safe operation on CPU IFR register).
12. Clear the PIEACK bit for the PIE group.
13. Enable global interrupts.
1.5.4.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU
Figure 1-8 shows the flow with the steps shown in circled numbers. Following the diagram, the steps are
described.
2
PIE
1
interrupt
flag
Peripheral
IE/IF
PIEIFRx.1
latch
Vector
8 interrupts
per group
Peripheral
IE/IF
PIEIFRx.8
latch
Vector
1. Any peripheral or external interrupt within the PIE group generates an interrupt. If interrupts are
enabled within the peripheral module then the interrupt request is sent to the PIE module.
2. The PIE module recognizes that interrupt y within PIE group x (INTx.y) has asserted an interrupt and
the appropriate PIE interrupt flag bit is latched: PIEIFRx.y = 1.
3. For the interrupt request to be sent from the PIE to the CPU, both of the following conditions must be
true:
a. The proper enable bit must be set (PIEIERx.y = 1) and
b. The PIEACKx bit for the group must be clear.
108
System Control and Interrupts
Figure 1-8. Multiplexed Interrupt Request Flow
3a
PIE
interrupt
enable
Highest
3b
PIEIERx.1
PIE group
0
acknowledge
1
PIEACKx
0
1
Search order
highest to
lowest
Lowest
PIEIERx.8
Vector is fetched
only after CPU
interrupt logic
0
has recognized
1
the interrupt
0
1
Copyright © 2012–2019, Texas Instruments Incorporated
4
5
1
1=valid Int
Pulse
0
gen IFRx
latch
9
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
6 7
IERx INTM
8
0 0
1 1
CPU CPU
interrupt
logic
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