If1 Message Control Register (Can If1Mctl) [Offset = 0X10C]; If2 Message Control Register (Can If2Mctl) [Offset = 0X12C]; If1 And If2 Message Control Registers Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

CAN Control Registers
Figure 23-38. IF1 Message Control Register (CAN IF1MCTL) [offset = 0x10C]
31
15 14 13 12
New Msg Int UMask
Dat Lst Pnd
R/WP- R/WP- R/WP- R/WP-
0 0 0 0
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset
Figure 23-39. IF2 Message Control Register (CAN IF2MCTL) [offset = 0x12C]
31
15 14 13 12
New Msg Int UMask
Dat Lst Pnd
R/WP- R/WP- R/WP- R/WP-
0 0 0 0
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset
Table 23-21. IF1 and IF2 Message Control Registers Field Descriptions
Bit Field
31-16 Reserved
15 NewDat
14 MsgLst
13 IntPnd
12 UMask
11 TxIE
10 RxIE
9 RmtEn
1560
M3 Controller Area Network (CAN)
11 10 9
TxIE RxIE Rmt
En
R/WP- R/WP- R/WP- R/WP-
0 0 0
11 10 9
TxIE RxIE Rmt
En
R/WP- R/WP- R/WP- R/WP-
0 0 0
Value Description
Reserved
New Data
0 No new data has been written into the data portion of this message object by the message handler
since the last time when this flag was cleared by the CPU.
1 The message handler or the CPU has written new data into the data portion of this message object.
Message Lost (only valid for message objects with direction = receive)
0 No message lost since the last time when this bit was reset by the CPU.
1 The message handler stored a new message into this object when NewDat was still set, so the
previous message has been overwritten.
Interrupt Pending
0 This message object is not the source of an interrupt.
1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register
will point to this message object if there is no other interrupt source with higher priority.
Use Acceptance Mask
0 Mask ignored
1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering
If the UMask bit is set to one, the message object's mask bits have to be programmed during
initialization of the message object before MsgVal is set to one.
Transmit Interrupt Enable
0 IntPnd will not be triggered after the successful transmission of a frame.
1 IntPnd will be triggered after the successful transmission of a frame.
Receive Interrupt Enable
0 IntPnd will not be triggered after the successful reception of a frame.
1 IntPnd will be triggered after the successful reception of a frame.
Remote Enable
0 At the reception of a remote frame, TxRqst is not changed.
1 At the reception of a remote frame, TxRqst is set.
Note: See Section 23.11.8
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7 6
Tx EoB Reserved
Rqst
R/WP- R-0
0 0
Reserved
R-0
8 7 6
Tx EoB Reserved
Rqst
R/WP- R-0
0 0
for details on the setup of RmtEn and UMask for remote frames.
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
4 3
DLC[3:0]
R/WP-0
4 3
DLC[3:0]
R/WP-0
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