Usb Transmit Control And Status Endpoint N High Register (Usbtxcsrh[N]) In Otg B/Device Mode; Usb Transmit Control And Status Endpoint N High Register (Usbtxcsrh[N]) In Otg B/Device Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 18-46. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
Bit Field Value
0 DT
The USBTXCSRH[n] registers in OTG B/Device Mode are shown in
Table 18-47.
Figure 18-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
7 6
AUTOSET ISO
R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-47. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
Bit Field Value
7 AUTOSET
0
1
6 ISO
0
1
5 MODE
0
1
4 DMAEN
0
1
3 FDT
0
1
2 DMAMOD
0
1
0 Reserved 0
SPRUH22I – April 2012 – Revised November 2019
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in OTG A/Host Mode Field Descriptions (continued)
Description
Data Toggle. When read, this bit indicates the current state of the transmit endpoint data toggle.
If DTWE is High, this bit can be written with the required setting of the data toggle. If DTWE is Low, any
value written to this bit is ignored. Care should be taken when writing to this bit as it should only be
changed to RESET the transmit endpoint.
in OTG B/Device Mode
5 4
MODE DMAEN
R/W-0 R/W-0
in OTG B/Device Mode Field Descriptions
Description
Auto Set
The TXRDY bit must be set manually.
Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in
USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is
loaded, then the TXRDY bit must be set manually.
Isochronous Transfers
Enables the transmit endpoint for bulk or interrupt transfers.
Enables the transmit endpoint for isochronous transfers.
Mode
Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive
transactions.
Enables the endpoint direction as RX.
Enables the endpoint direction as TX.
DMA Request Enable
Note: Three TX and three /RX endpoints can be connected to the μDMA module. If this bit is set for a
particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
Disables the μDMA request for the transmit endpoint.
Enables the μDMA request for the transmit endpoint.
Force Data Toggle
No effect
Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to
communicate rate feedback for isochronous endpoints.
DMA Request Mode
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
An interrupt is generated after every μDMA packet transfer.
An interrupt is generated only after the entire μDMA transfer is complete.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 18-44
3 2
FDT DMAMOD
R/W-0 R/W-0
M3 Universal Serial Bus (USB) Controller
Register Descriptions
and described in
1 0
Reserved
R-0
1343