Usb Test Mode Register (Usbtest), Offset 0X00F; Usb Test Mode Register (Usbtest) In Otg A/Host Mode; Usb Test Mode Register (Usbtest) In Otg B/Device Mode; Usb Test Mode Register (Usbtest) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

18.5.11 USB Test Mode Register (USBTEST), offset 0x00F

The USB test mode 8-bit register (USBTEST) is primarily used to put the USB controller into one of the
four test modes for operation described in the USB 2.0 Specification, in response to a SET FEATURE:
USBTESTMODE command. This register is not used in normal operation.
Note: Only one of these bits should be set at any time.
Mode(s): OTG A or Host
USBTEST in OTG A/Host Mode is shown in
Figure 18-15. USB Test Mode Register (USBTEST) in OTG A/Host Mode
7 6
FORCEH FIFOACC
R/W-0 R/W1S-0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 18-18. USB Test Mode Register (USBTEST) in OTG A/Host Mode Field Descriptions
Bit Field
7 FORCEH
6 FIFOACC
5 FORCEFS
4-0 Reserved
USBTEST in OTG B/Device Mode is shown in
Figure 18-16. USB Test Mode Register (USBTEST) in OTG B/Device Mode
7 6
Reserved FIFOACC
R-0 R/W1S-0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 18-19. USB Test Mode Register (USBTEST) in OTG B/Device Mode Field Descriptions
Bit Field
7 Reserved
6 FIFOACC
1316
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-15
5 4
FORCEFS
R/W-0
Value Description
Force Host Mode. While in this mode, status of the bus connection may be read using the DEV
bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit.
0 No effect
1 Forces the USB controller to enter Host mode when the SESSION bit is set, regardless of
whether the USB controller is connected to any peripheral. The state of the USB0DP and
USB0DM signals is ignored. The USB controller then remains in Host mode until the SESSION
bit is cleared, even if a Device is disconnected. If the FORCEH bit remains set, the USB
controller re-enters Host mode the next time the SESSION bit is set.
FIFO Access
0 No effect
1 Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO.
Force Full-Speed Mode
0 The USB controller operates at Low Speed.
1 Forces the USB controller into Full-Speed mode upon receiving a USB RESET.
0 Reserved
5 4
FORCEFS
R/W-0
Value Description
Force Host Mode. While in this mode, status of the bus connection may be read using the DEV
bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit.
FIFO Access
0 No effect
1 Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO.
Copyright © 2012–2019, Texas Instruments Incorporated
and described in
Reserved
R-0
Figure 18-16 and described in
Reserved
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 18-18.
0
Table 18-19.
0
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