Adc Reference/Gain Trim Register (Adcreftrim) (Address Offset 40H); Adc Offset Trim Register (Adcofftrim) (Address Offset 41H); Adc Reference/Gain Trim Register (Adcreftrim) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 10-21. ADC SOC0 - SOC15 Control Registers (ADCSOCxCTL) Register Field
Bit Field
5-0 ACQPS
Other invalid selections: 10h, 11h, 12h, 13h, 14h, 1Dh, 1Eh, 1Fh, 20h, 21h, 2Ah, 2Bh, 2Ch, 2Dh, 2Eh, 37h, 38h, 39h, 3Ah, 3Bh
NOTE: Also configure the TRIGxSEL registers for which trigger source will be tied to each ADC
trigger.
10.3.11.6 ADC Calibration Registers
NOTE: The following ADC Calibration Registers are EALLOW protected.
Figure 10-37. ADC Reference/Gain Trim Register (ADCREFTRIM) (Address Offset 40h)
15 13 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-22. ADC Reference/Gain Trim Register (ADCREFTRIM) Field Descriptions
Bit Field
15-13 Reserved
12-8 EXTREF_FINE_TRIM
7-4 BG_COARSE_TRIM
3-0 BG_FINE_TRIM
Figure 10-38. ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 41h)
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Descriptions (continued)
Value Description
SOCx Acquisition Prescale. Controls the sample and hold window for SOCx. Minimum value
allowed is 6.
00h Invalid selection.
01h Invalid selection.
02h Invalid selection.
03h Invalid selection.
04h Invalid selection.
05h Invalid selection.
06h Sample window is 7 cycles long (6 + 1 clock cycles).
07h Sample window is 8 cycles long (7 + 1 clock cycles).
08h Sample window is 9 cycles long (8 + 1 clock cycles).
09h Sample window is 10 cycles long (9 + 1 clock cycles).
... ...
3Fh Sample window is 64 cycles long (63 + 1 clock cycles).
EXTREF_FINE_TRIM
R/W-0
Value Description
Reserved
ADC External reference Fine Trim. These bits should not be modified after device boot
code loads them with the factory trim setting.
ADC Internal Bandgap Fine Trim. These bits should not be modified after device boot code
loads them with the factory trim setting.
ADC Internal Bandgap Coarse Trim. A maximum value of 30 is supported. These bits
should not be modified after device boot code loads them with the factory trim setting.
9
Copyright © 2012–2019, Texas Instruments Incorporated
8 7
BG_COARSE_TRIM
R/W-0
8
OFFTRIM
Analog-to-Digital Converter (ADC)
4 3
BG_FINE_TRIM
R/W-0
R/W-0
Analog Subsystem
0
0
887