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25.1 Overview
The Concerto™ implementation of the Cortex-M3 processor peripherals include:
•
SysTick
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control
mechanism.
•
Nested Vectored Interrupt Controller (NVIC)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
•
System Control Block (SCB)
Provides system implementation information and system control, including configuration, control, and
reporting of system exceptions.
•
Memory Protection Unit (MPU)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions, and
exporting memory attributes to the system.
Note: This feature is disabled on these devices.
Table 25-1
shows the address map of the private peripheral bus (PPB). Some peripheral register regions
are split into two address regions, as indicated by two addresses listed.
Address
0xE000.E010-0xE000.E01F
0xE000.E100-0xE000.E4EF
0xE000.EF00-0xE000.EF03
0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
0xE000.ED90-0xE000.EDB8
25.2 Functional Description
This section provides information on the Concerto implementation of the Cortex-M3 processor peripherals:
SysTick, NVIC, SCB and MPU.
25.2.1 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write,
decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways, for example as:
•
An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
•
A high-speed alarm timer using the system clock.
•
A variable rate alarm or signal timer; the duration is range-dependent on the reference clock used and
the dynamic range of the counter.
•
A simple counter used to measure time to completion and time used.
•
An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL
control and status register can be used to determine if an action completed within a set duration, as
part of a dynamic clock management control loop.
The timer consists of three registers:
•
SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the
counter, enable the SysTick interrupt, and determine counter status.
•
SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's
SPRUH22I – April 2012 – Revised November 2019
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Table 25-1. Core Peripheral Register Regions
Core Peripheral
System Timer
Nested Vectored Interrupt Controller
System Control Block
Memory Protection Unit
Copyright © 2012–2019, Texas Instruments Incorporated
Overview
1599
Cortex-M3 Peripherals
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