Receiver Data Buffer Registers (Scirxemu, Scirxbuf); Register Scirxst Bit Associations - Address 7055H; Emulation Data Buffer Register (Scirxemu) - Address 7056H; Sci Receive Data Buffer Register (Scirxbuf) - Address 7057H - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 13-18. Register SCIRXST Bit Associations — Address 7055h
7
RX ERROR RXRDY
RXRDY or BRKDT causes an interrupt
if RX/BK INT ENA (SCICTL2.1) = 1

13.3.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF)

Received data is transferred from RXSHF to SCIRXEMU and SCIRXBUF. When the transfer is complete,
the RXRDY flag (bit SCIRXST.6) is set, indicating that the received data is ready to be read. Both
registers contain the same data; they have separate addresses but are not physically separate buffers.
The only difference is that reading SCIRXEMU does not clear the RXRDY flag; however, reading
SCIRXBUF clears the flag.
13.3.7.1 Emulation Data Buffer (SCIRXEMU)
Normal SCI data-receive operations read the data received from the SCIRXBUF register. The SCIRXEMU
register is used principally by the emulator (EMU) because it can continuously read the data received for
screen updates without clearing the RXRDY flag. SCIRXEMU is cleared by a system reset.
This is the register that should be used in an emulator watch window to view the contents of the
SCIRXBUF register.
SCIRXEMU is not physically implemented; it is just a different address location to access the SCIRXBUF
register without clearing the RXRDY flag.
Figure 13-19. Emulation Data Buffer Register (SCIRXEMU) — Address 7056h
7 6
ERXDT7 ERXDT6
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
13.3.7.2 Receiver Data Buffer (SCIRXBUF)
When the current data received is shifted from RXSHF to the receiver buffer, flag bit RXRDY is set and
the data is ready to be read. If the RX/BK INT ENA bit (SCICTL2.1) is set, this shift also causes an
interrupt. When SCIRXBUF is read, the RXRDY flag is reset. SCIRXBUF is cleared by a system reset.
Figure 13-20. SCI Receive Data Buffer Register (SCIRXBUF) — Address 7057h
15 14
(1) (1)
SCIFFFE SCIFFPE
R−0 R−0
7 6
RXDT7 RXDT6
R−0 R−0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
Applicable only if the FIFO is enabled.
SPRUH22I – April 2012 – Revised November 2019
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6 5
BRKDT
RX ERROR = 1 when any of bits 5 through 2 is a 1 value
5 4
ERXDT5 ERXDT4
R-0 R-0
13
5 4
RXDT5 RXDT4
R−0 R−0
Copyright © 2012–2019, Texas Instruments Incorporated
4 3
FE OE PE
3
ERXDT3 ERXDT2
R-0
Reserved
R−0
3
RXDT3 RXDT2
R−0
C28 Serial Communications Interface (SCI)
SCI Registers
2 1 0
RXWAKE
Reserved
2 1
ERXDT1
R-0 R-0
2 1
RXDT1
R−0 R−0
0
ERXDT0
R-0
8
0
RXDT0
R−0
1001