C28 Nmi Flag Force (Cnmiflgfrc) Register; C28 Nmi Watchdog Counter (Cnmiwdcnt) Register; C28 Nmi Flag Force (Cnmiflgfrc) Register Field Descriptions; C28 Nmi Watchdog Counter (Cnmiwdcnt) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers

1.13.5.10 C28 NMI Flag Force (CNMIFLGFRC) Register

15
7 6
Reserved ACIBERR
R-0:0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-78. C28 NMI Flag Force (CNMIFLGFRC) Register Field Descriptions
Bit Field
15-7 Reserved
6 ACIBERR
5-3 Reserved
2 C28RAMUNCER
R
1 CLOCKFAIL
0 Reserved

1.13.5.11 C28 NMI Watchdog Counter (CNMIWDCNT) Register

15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-79. C28 NMI Watchdog Counter (CNMIWDCNT) Register Field Descriptions
Bit Field
15-0 NMIWDCNT
206
System Control and Interrupts
Figure 1-67. C28 NMI Flag Force (CNMIFLGFRC) Register
5
Reserved
R-0
Value Description
Reserved
CIB Error NMI Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Clears the corresponding flag bit in the NMIFLG register.
Reserved
C28 RAM Uncorrectable Error NMI Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Clears the corresponding flag bit in the NMIFLG register.
Clock Fail NMI Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Clears the corresponding flag bit in the NMIFLG register.
Reserved
Figure 1-68. C28 NMI Watchdog Counter (CNMIWDCNT) Register
Value Description
NMI Watchdog Counter
This 16-bit incremental counter will start incrementing whenever any one of the enabled "FAIL"
flags are set. If the counter reaches the period value, an NMIRS signal is fired which will then reset
the C28 CPU and sub-system. See
will reset to zero when it reaches the period value and will then restart counting if any of the
enabled "NMI" flags are set.
If no enabled "NMI" flag is set, then the counter will reset to zero and remain at zero until an
enabled "NMI" flag is set.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
3
C28RAMUNCERR
R/W-0
NMIWDCNT
R-0:0
Section 1.3 for more details on the reseT behavior. The counter
SPRUH22I – April 2012 – Revised November 2019
2 1
CLOCKFAIL
R/W-0
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8
0
Reserved
R-0:0
0