Mastership Of Clock Configuration Registers For Different States Of Clock Configuration Semaphore - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 1-27. Mastership of Clock Configuration Registers for Different States of Clock Configuration
M3 should write "10" to gain mastership of
the clock configuration registers
M3 should write "00" to relinquish
mastership
Semaphore state "10"
Clock configuration registers are
mapped to the M3
C28x will not be able to gain
mastership over the clock configuration
registers when the semaphore is in
this state
By default at reset, clock configuration registers are mapped to the M3 with a semaphore value of "00".
Even though clock configuration registers are mapped to the M3 by default, the M3 should gain
mastership by writing a value of "10" in the MCLKREQUEST register when the M3 wants to configure the
clock settings and perform any operations at that clock frequency. This prevents the C28x from grabbing
mastership over clock configuration registers when the M3 is configuring the clock settings and executing
at that frequency.
Once the M3 is done with configuring the clock settings and any operations that it wants to perform at that
configured frequency, it should release mastership of the clock configuration registers by writing a value of
"00" in the MCLKREQUEST semaphore so that the C28x can request mastership over clock control
registers when needed. If the user's application is designed in such a way that the C28x is not allowed to
modify the clock settings and only the M3 configures the clock settings for the C28x as well (for flash
erase/program or even for normal application execution), then it is suggested that the M3 should keep
mastership over clock configuration registers by writing a value of "10" in the MCLKREQUEST register
and not setting it back to "00".
If the user's application is designed in such a way that the C28x is allowed to configure the clock settings,
then the C28x should gain mastership of the clock configuration registers by writing a value of "01" in the
CCLKREQUEST register when the C28x wants to configure clock settings. This prevents the M3 from
writing to clock configuration registers when the C28x is configuring them.
When C28x is configuring the Clock settings, the PLL has to be powered down before changing the PLL
multiplier (if the PLL is being used in the application). PLL can be turned on once the PLL multiplier is
configured. Below is the required sequence for PLL configuration from C28x:
1. Make C28x gain mastership of clock configuration registers using the clock configuration semaphore
2. Bypass the PLL
3. Power down the PLL (this is not required when configuring clocks from M3)
4. Maximize the clock dividers
5. Modify the PLL multiplier
6. Power on the PLL
7. Wait for the PLL to lock
8. Put the PLL back into the clock path
9. Modify the clock dividers as desired by the application
SPRUH22I – April 2012 – Revised November 2019
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Semaphore
Semaphore state "00"
(Default at Reset)
Clock configuration registers
are mapped to the M3
Not allowed
Not allowed
Copyright © 2012–2019, Texas Instruments Incorporated
Inter Processor Communications (IPC)
C28x should write "01" to gain mastership of
the clock configuration registers
C28x should write "00" to relinquish
mastership
Semaphore state "01"
Clock configuration registers are
mapped to the C28x
M3 will not be able to gain
mastership over the clock configuration
registers when the semaphore is in
this state
System Control and Interrupts
before
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