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Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the interrupted
program. This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing the
exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating
which stack pointer corresponds to the stack frame and what operation mode the processor was in before
the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status of the
earlier exception.
24.7.7.2 Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
•
An LDM or POP instruction that loads the PC
•
A BX instruction using any register
•
An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on
this value to detect when the processor has completed an exception handler. The lowest four bits of this
value provide information on the return stack and processor mode.
values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
EXC_RETURN[31:0]
0xFFFF.FFF0
0xFFFF.FFF1
0xFFFF.FFF2 - 0xFFFF.FFF8
0xFFFF.FFF9
0xFFFF.FFFA - 0xFFFF.FFFC
0xFFFF.FFFD
0xFFFF.FFFE - 0xFFFF.FFFF
SPRUH22I – April 2012 – Revised November 2019
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Figure 24-15. Exception Stack Frame
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Table 24-18. Exception Return Behavior
Description
Reserved
Return to Handler mode.Exception return uses state from
MSP.Execution uses MSP after return.
Reserved
Return to Thread mode.Exception return uses state from
MSP.Execution uses MSP after return.
Reserved
Return to Thread mode.Exception return uses state from
PSP.Execution uses PSP after return.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Pre-IRQ top of stack
IRQ top of stack
Table 24-18
shows the EXC_RETURN
Exception Model
1591
Cortex-M3 Processor
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