Non-Master Access Violation Force Register (Cnmavfrc); Non-Master Access Violation Flag Clear Register (Cnmavclr); Non-Master Access Violation Force Register (Cnmavfrc) Field Descriptions; Non-Master Access Violation Flag Clear Register (Cnmavclr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.2.4.15 Non-Master Access Violation Force Register (CNMAVFRC)

Figure 5-67. Non-Master Access Violation Force Register (CNMAVFRC)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-72. Non-Master Access Violation Force Register (CNMAVFRC) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH

5.2.4.16 Non-Master Access Violation Flag Clear Register (CNMAVCLR)

Figure 5-68. Non-Master Access Violation Flag Clear Register (CNMAVCLR)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-73. Non-Master Access Violation Flag Clear Register (CNMAVCLR) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH
SPRUH22I – April 2012 – Revised November 2019
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Reserved
R-0
Value Description
Reserved
Non-Master CPU Write Access Violation Force. Any reads to this bit will return a 0.
0 No effect.
1 Sets the CPUFETCH flag in the CNMAVFLG register.
Non-Master DMA Write Access Violation Force. Any reads to this bit will return a 0.
0 No effect.
1 Sets the DMAWRITE flag in the CNMAVFLG register.
Non-Master CPU Fetch Access Violation Force. Any reads to this bit will return a 0.
0 No effect.
1 Sets the CPUFETCH flag in the CNMAVFLG register.
Reserved
R-0
Value Description
Reserved
Non-Master CPU Write Access Violation Clear. Any reads to this bit will return a 0.
0 No effect.
1 Clears the corresponding non-master CPU write access violation flag.
Non-Master DMA Write Access Violation Clear. Any reads to this bit will return a 0.
0 No effect.
1 Clears the corresponding non-master DMA write access violation flag.
Non-Master CPU Fetch Access Violation Clear. Any reads to this bit will return a 0.
0 No effect.
1 Clears the corresponding non-master CPU fetch access violation flag.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
CPUWRITE
R/W=1-0
Reserved
R-0
3 2
CPUWRITE
R/W=1-0
RAM Control Module Registers
16
1 0
DMAWRITE CPUFETCH
R/W=1-0 R/W=1-0
16
1 0
DMAWRITE CPUFETCH
R/W=1-0 R/W=1-0
Internal Memory
487