M3Nmi Watchdog Counter (Mnmiwdcnt) Register; M3Nmi Watchdog Period (Mnmiwdprd) Register; M3Nmi Watchdog Counter (Mnmiwdcnt) Register Field Descriptions; M3Nmi Watchdog Period (Mnmiwdprd) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

System Control Registers

Table 1-72. M3NMI Flag Force (MNMIFLGFRC) Register Field Descriptions (continued)

1.13.5.5 M3NMI Watchdog Counter (MNMIWDCNT) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-73. M3NMI Watchdog Counter (MNMIWDCNT) Register Field Descriptions

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-74. M3NMI Watchdog Period (MNMIWDPRD) Register Field Descriptions

System Control and Interrupts

M3 BIST Error Flag.

Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI

Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers.

Clock Fail NMI Flag Force

Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.

Sets the corresponding flag bit in the NMIFLG register.

Figure 1-62. M3NMI Watchdog Counter (MNMIWDCNT) Register

NMI Watchdog Counter

This 16-bit incremental counter will start incrementing whenever any one of the enabled "NMI" flags

are set. If the counter reaches the period value, an NMIRS signal is fired which will then reset the

full device. See

when it reaches the period value and will then restart counting if any of the enabled "NMI" flags are

Normally, the software would respond to the NMI interrupt generated and clear the offending

FLAG(s) before the NMI watchdog triggers a reset. In some situations, the software may decide to

allow the watchdog to reset the device anyway.

If no enabled "NMI" flag is set, then the counter will reset to zero and remain at zero until an

enabled "NMI" flag is set. The counter is clocked at the M3 SSCLK rate.

Figure 1-63. M3NMI Watchdog Period (MNMIWDPRD) Register

M3 NMI Watchdog Period

This 16-bit value contains the period value at which a reset is generated when the watchdog

counter matches. At reset, this value is set at the maximum. The software can decrease the period

value at initialization time.

Writing a PERIOD value that is smaller then the current counter value will automatically force an

NMIRS to the M3 and hence reset the watchdog counter.

for more details on the reset behavior. The counter will reset to zero

SPRUH22I – April 2012 – Revised November 2019

Submit Documentation Feedback

Table of Contents