Programming Model; Processor Mode And Privilege Levels For Software Execution; Stacks; Register Map - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Programming Model

provides up to eight different regions and an optional predefined background region (see Memory
Protection Unit (MPU) in the Cortex-M3 Peripherals chapter).
24.4 Programming Model
This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.

24.4.1 Processor Mode and Privilege Levels for Software Execution

The Cortex-M3 processor has two modes of operation:
• Thread mode
Used to execute application software. The processor enters thread mode when it comes out of reset.
• Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to thread
mode.
In addition, the processor has two privilege levels:
• Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
• Privileged
In this mode, software can use all the instructions and has access to all resources.
In thread mode, the CONTROL register controls whether software execution is privileged or unprivileged.
In handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to
transfer control to privileged software.

24.4.2 Stacks

The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item
on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks: the
main stack and the process stack, with independent copies of the stack pointer.
In thread mode, the CONTROL register controls whether the processor uses the main stack or the
process stack. In handler mode, the processor always uses the main stack. The options for processor
operations are shown in
Table 24-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Thread
Handler

24.4.3 Register Map

Figure 24-2 shows the Cortex-M3 register set.
not memory mapped and are accessed by register name, so the base address is not applicable and there
is no offset.
1570
Cortex-M3 Processor
Table 24-1.
Use
Applications
Exception handlers
Table 24-2
Copyright © 2012–2019, Texas Instruments Incorporated
Privilege Level
Privileged or unprivilegeda
Always privileged
lists the core registers. The core registers are
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Stack Used
Main stack or process stacka
Main stack
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