Dma Control Register (Dmactrl); Dma Control Register (Dmactrl) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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DST_ADDR_SHADOW

DST_BEG_ADDR

DMA Channel 2 Registers

Same as above

DMA Channel 3 Registers

Same as above

DMA Channel 4 Registers

Same as above

DMA Channel 5 Registers

Same as above

DMA Channel 6 Registers

Same as above

11.8.1 DMA Control Register (DMACTRL) — EALLOW Protected

The DMA control register (DMACTRL) is shown in

LEGEND: R0/S = Read 0/Set; R = Read only; -n = value after reset

PRIORITYRESET

SPRUH22I – April 2012 – Revised November 2019

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Table 11-2. DMA Register Summary

Active Destination Begin and Current Address Pointer Registers

Figure 11-8. DMA Control Register (DMACTRL)

Table 11-3. DMA Control Register (DMACTRL) Field Descriptions

The priority reset bit resets the round-robin state machine when a 1 is written. Service starts

from the first enabled channel. Writes of 0 are ignored and this bit always reads back a 0.

When a 1 is written to this bit, any pending burst transfer completes before resetting the

channel priority machine. If CH1 is configured as a high priority channel, and this bit is

written to while CH1 is servicing a burst, the CH1 burst is completed and then any lower

priority channel burst is also completed (if CH1 interrupted in the middle of a burst), before

the state machine is reset.

In case CH1 is high priority, the state machine restarts from CH2 (or the next highest

enabled channel).

and described in

C28 Direct Memory Access (DMA) Module

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