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Table 15-27. Register Bits Used to Set the Receive Frame Length (continued)
Register
Bit
Name
RCR2
14-8
RFRLEN2
15.8.9.1 Selected Frame Length
The receive frame length is the number of serial words in the receive frame. Each frame can have one or
two phases, depending on value that you load into the RPHASE bit.
If a single-phase frame is selected (RPHASE = 0), the frame length is equal to the length of phase 1. If a
dual-phase frame is selected (RPHASE = 1), the frame length is the length of phase 1 plus the length of
phase 2.
The 7-bit RFRLEN fields allow up to 128 words per phase. See
calculate the frame length. This length corresponds to the number of words or logical time slots or
channels per frame-synchronization pulse.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For the
example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.
RPHASE
0
0 ≤ RFRLEN1 ≤ 127
1
0 ≤ RFRLEN1 ≤ 127
15.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function
The RFIG bit (see
Table 15-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore
Register
Bit
Name
RCR2
2
RFIG
15.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
received, this pulse is treated as an unexpected frame-synchronization pulse.
When RFIG = 1, reception continues, ignoring the unexpected frame-synchronization pulses.
SPRUH22I – April 2012 – Revised November 2019
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Function
Receive frame length 2
If a dual-phase frame is selected, (RFRLEN2 + 1) is the number of serial
words in phase 2 of the receive frame.
RFRLEN2 = 000 0000
RFRLEN2 = 000 0001
|
|
RFRLEN2 = 111 1111
Table 15-28. How to Calculate the Length of the Receive Frame
RFRLEN1
0 ≤ RFRLEN2 ≤ 127
Table
15-29) controls the receive frame-synchronization ignore function.
Function
Receive frame-synchronization ignore
RFIG = 0
An unexpected receive frame-synchronization pulse causes the
McBSP to restart the frame transfer.
RFIG = 1
The McBSP ignores unexpected receive frame-synchronization
pulses.
Copyright © 2012–2019, Texas Instruments Incorporated
1 word in phase 2
2 words in phase 2
|
|
128 words in phase 2
Table 15-28
RFRLEN2
Frame Length
Don't care
(RFRLEN1 + 1) words
(RFRLEN1 + 1) + (RFRLEN2 + 1) words
Function
C28 Multichannel Buffered Serial Port (McBSP)
Receiver Configuration
Reset
Type
Value
R/W
000 0000
for a summary of how to
Reset
Type
Value
R/W
0
1083
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