Spi Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

Enhanced SPI Module Overview

12 SPI module control registers: Located in the control register frame beginning at address 7040h.

NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7−0), and the upper byte

(15−8) is read as zeros. Writing to the upper byte has no effect.

Enhanced Features:

4 -level transmit/receive FIFO

Delayed transmit control

12.1.1 SPI Block Diagram

is a block diagram of the SPI in slave mode, showing the basic control blocks available on the

C28 Serial Peripheral Interface (SPI)

SPRUH22I – April 2012 – Revised November 2019

Submit Documentation Feedback

Table of Contents