Accessing Concatenated Register Values; Initialization And Configuration; One-Shot/Periodic Timer Mode - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description

2.3.4 Accessing Concatenated Register Values

The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in the
GPTM Configuration (GPTMCFG) register. In both configurations, certain registers are concatenated to
form pseudo 32-bit registers. These registers include:
• GPTM Timer A Interval Load (GPTMTAILR) register [15:0]
• GPTM Timer B Interval Load (GPTMTBILR) register [15:0]
• GPTM Timer A (GPTMTAR) register [15:0]
• GPTM Timer B (GPTMTBR) register [15:0]
• GPTM Timer A Value (GPTMTAV) register [15:0]
• GPTM Timer B Value (GPTMTBV) register [15:0]
• GPTM Timer A Match (GPTMTAMATCHR) register [15:0]
• GPTM Timer B Match (GPTMTBMATCHR) register [15:0]
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both
GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
2.4

Initialization and Configuration

To use a GPTM, the appropriate TIMERn bit must be set in the RCGC1 register. If using any CCP pins,
the clock to the appropriate GPIO module must be enabled via the RCGC1 register (see the System
Control chapter).
To find out which GPIO port to enable, refer to the PMCn fields in the GPIOPCTL register to assign the
CCP signals to the appropriate pins (see the GPIOs chapter).
This section shows module initialization and configuration examples for each of the supported timer
modes.

2.4.1 One-Shot/Periodic Timer Mode

The GPTM is configured for one-shot and periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making any
changes.
2. Write the GPTM Configuration register (GPTMCFG) with a value of 0x0000.0000.
3. Configure the TnMR field in the GPTM Timer n Mode register (GPTMTnMR)
1. Write a value of 0x1 for one-shot mode.
2. Write a value of 0x2 for periodic mode.
4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register to
select whether to capture the value of the free-running timer at time-out, use an external trigger to start
counting, configure an additional trigger or interrupt, and count up or down.
5. Load the start value into the GPTM Timer n Interval Load register (GPTMTnILR).
6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask register (GPTMIMR).
7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting.
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the
status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register
(GPTMICR).
306
M3 General-Purpose Timers
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com