Interrupt 64-95 Clear Enable (Dis2) Register, Offset 0X188; Interrupt 64-95 Clear Enable (Dis2) Register; Interrupt 64-95 Clear Enable (Dis2) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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25.5.8 Interrupt 64-95 Clear Enable (DIS2) Register, offset 0x188

The Interrupt 64-95 Clear Enable (DIS2) register disables interrupts. Bit 0 corresponds to Interrupt 64; bit
31 corresponds to Interrupt 95. See the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-18. Interrupt 64-95 Clear Enable (DIS2) Register Field Descriptions
Bit Field
31-0 INT
SPRUH22I – April 2012 – Revised November 2019
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Figure 25-12. Interrupt 64-95 Clear Enable (DIS2) Register
Value Description
Interrupt Disable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the
EN2 register, disabling interrupt [n].
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INT
R/W-0
NVIC Register Descriptions
0
1615
Cortex-M3 Peripherals