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The μ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits
wide; the appropriate word length bits (RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be
set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame
phases does not have an 8-bit word length, companding continues as if the word length is 8 bits.
Figure 15-3
illustrates the companding processes. When companding is chosen for the transmitter,
compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is
encoded according to the specified companding law (A-law or μ-law). When companding is chosen for the
receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is
decoded to twos-complement format.
RSR1
DR
DX
15.1.5.1 Companding Formats
For reception, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1. The
receive sign-extension and justification mode specified in RJUST is ignored when companding is used.
For transmission using μ-law compression, the 14 data bits must be left-justified in DXR1 and that the
remaining two low-order bits are filled with 0s as shown in
µ-law format in DXR1
For transmission using A-law compression, the 13 data bits must be left-justified in DXR1, with the
remaining three low-order bits filled with 0s as shown in
A-law format in DXR1
15.1.5.2 Capability to Compand Internal Data
If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the
companding hardware can compand internal data. This can be used to:
•
Convert linear to the appropriate μ-law or A-law format
•
Convert μ-law or A-law to the linear format
•
Observe the quantization effects in companding by transmitting linear data and compressing and re-
expanding this data. This is useful only if both XCOMPAND and RCOMPAND enable the same
companding format.
Figure 15-6
shows two methods by which the McBSP can compand internal data. Data paths for these
two methods are used to indicate:
•
When both the transmit and receive sections of the serial port are reset, DRR1 and DXR1 are
connected internally through the companding logic. Values from DXR1 are compressed, as selected by
XCOMPAND, and then expanded, as selected by RCOMPAND. RRDY and XRDY bits are not set.
However, data is available in DRR1 within four CPU clocks after being written to DXR1.
The advantage of this method is its speed. The disadvantage is that there is no synchronization
available to the CPU and DMA to control the flow. DRR1 and DXR1 are internally connected if the
(X/R)COMPAND bits are set to 10b or 11b (compand using μ-law or A-law).
SPRUH22I – April 2012 – Revised November 2019
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Figure 15-3. Companding Processes
8
RBR1
Expand
8
Compress
XSR1
Figure 15-4. μ-Law Transmit Data Companding Format
Figure 15-5. A-Law Transmit Data Companding Format
Copyright © 2012–2019, Texas Instruments Incorporated
16
DRR1
To CPU or DMA controller
16
DXR1
From CPU or DMA controller
Figure
15-4.
15-2
Value
Figure
15-5.
15-3
2-0
Value
000
C28 Multichannel Buffered Serial Port (McBSP)
Overview
1-0
00
1041
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