System Handler Control And State (Syshndctrl) Register; System Handler Control And State (Syshndctrl) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Block (SCB) Register Descriptions
25.6.11 System Handler Control and State (SYSHNDCTRL) Register, offset 0xD24
Note: This register can only be accessed from privileged mode.
The System Handler Control and State (SYSHNDCTRL) register enables the system handlers, and
indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions
as well as the active status of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard
fault.
This register can be modified to change the pending or active status of system exceptions. An OS kernel
can write to the active bits to perform a context switch that changes the current exception type.
Software that changes the value of an active bit in this register without correct
adjustment to the stacked content can cause the processor to generate a fault
exception. Ensure software that writes to this register retains and subsequently
restores the current active status.
If the value of a bit in this register must be modified after enabling the system
handlers, a read-modify-write procedure must be used to ensure that only the
required bit is modified
.
Figure 25-42. System Handler Control and State (SYSHNDCTRL) Register
31
23
15 14
SVC BUSP
R/W-0 R/W-0
7 6
SVCA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-49. System Handler Control and State (SYSHNDCTRL) Register Field Descriptions
Bit Field
31-19 Reserved
18 USAGE
17 BUS
16 MEM
1640
Cortex-M3 Peripherals
Reserved
R-0
13 12
MEMP USAGEP
R/W-0 R/W-0
4
Reserved
R-0
Value Description
Reserved
Usage Fault Enable
0 Disables the usage fault exception.
1 Enables the usage fault exception.
Bus Fault Enable
0 Disables the bus fault exception.
1 Enables the bus fault exception.
Memory Management Fault Enable
0 Disables the memory management fault exception.
1 Enables the memory management fault exception.
Copyright © 2012–2019, Texas Instruments Incorporated
CAUTION
Reserved
R-0
19 18
USAGE
R/W-0
11 10
TICK PNDSV
R/W-0 R/W-0
3 2
USGA Reserved
R/W-0 R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
24
17 16
BUS MEM
R/W-0 R/W-0
9 8
Reserved MON
R-0 R/W-0
1 0
BUSA MEMA
R/W-0 R/W-0
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