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NVIC Register Descriptions
25.5.6 Interrupt 0-31 Clear Enable (DIS0) Register, offset 0x180
The Interrupt 0-31 Clear Enable (DIS0) register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31
corresponds to Interrupt 31.See the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-16. Interrupt 0-31 Clear Enable (DIS0) Register Field Descriptions
Bit
Field
31-0
INT
25.5.7 Interrupt 32-63 Clear Enable (DIS1) Register, offset 0x184
The Interrupt 32-63 Clear Enable (DIS1) register disables interrupts. Bit 0 corresponds to Interrupt 32; bit
31 corresponds to Interrupt 63. See the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-17. Interrupt 32-63 Clear Enable (DIS1) Register Field Descriptions
Bit
Field
31-0
INT
1614
Cortex-M3 Peripherals
Figure 25-10. Interrupt 0-31 Clear Enable (DIS0) Register
Value
Description
Interrupt Disable
0
On a read, indicates the interrupt is disabled. On a write, no effect.
1
On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the
EN0 register, disabling interrupt [n].
Figure 25-11. Interrupt 32-63 Clear Enable (DIS1) Register
Value
Description
Interrupt Disable
0
On a read, indicates the interrupt is disabled. On a write, no effect.
1
On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the
EN1 register, disabling interrupt [n].
Copyright © 2012–2019, Texas Instruments Incorporated
INT
R/W-0
INT
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
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