M-Boot Rom Version And Checksum Information - Texas Instruments Concerto F28M35 Series Technical Reference Manual

M-Boot ROM Description
Vector Name (Number)
Bus Fault (5)
Usage Fault (6)
Reserved (7-10)
SVCall (11)
DebugMonitor(12)
Reserved (13)
PendSV (14)
SysTick (15)
GPIOPort-A (16)
Other programmable Interrupts
(17 – 107
As indicated in the table above:
• On reset, Stack Pointer will point to RAM location 0x20004900. RAM locations 0x20004900-
0x20004000 are reserved for boot ROM.
• ResetIsr - is the function executed whenever M-Boot ROM is executed after reset.
• mbrom_nmi_interrupt_handler – is the function executed whenever there is an NMI during boot or as
long as the NVIC base address points to 0x00000000 in M-Boot ROM.
• mbrom_hard_fault_isr_handler – is the function executed whenever there is a HARD FAULT condition
detected by Cortext-M3 CPU during boot or as long as the NVIC base address points to 0x00000000
in M-Boot ROM.
– NOTE: Memory Management Fault, Bus Fault and Usage Fault exceptions are disabled by default
on reset in Cortex-M3 CPU and so is the case in M-Boot ROM. So if any of these errors occur
during M-Boot ROM execution, they end up triggering a Hard Fault Exception.
• SysTickIntHandler – is the function used by Ethernet bootloaders for timing during EMAC boot.
• GpioIntHander – is the function used by the UART bootloader for AutoBaud calculation.

6.5.3 M-Boot ROM Version and Checksum Information

M-Boot ROM contains a version number located at 0x010001B0 occupying two bytes. This version is
incremented each time M-Boot ROM code is modified. The next two bytes starting from 0x010001B2
contain the month and year (MM/YY in decimal) that the boot code was released. The next 0x84 bytes
contain a checksum value for M-Boot ROM. A proprietary checksum algorithm is used on this device to
allow boot ROM to be tested more efficiently. The checksum algorithm used is also embedded in ROM
and will be published along with the device's boot ROM sources.
Address
0x010001B0 – 0x010001B1
0x010001B2 – 0x010001B3
0x010001B4 – 0x01000238
6.5.4 M-Boot ROM RAM Initialization
RAM memories on the master subsystem and control subsystem on Concerto devices must be zero-
initialized before using the RAM for the first time to avoid any ECC and Parity errors. Refer to the Internal
Memory chapter for more details on RAM ECC and Parity.
542
ROM Code and Peripheral Booting
Table 6-2. M-Boot ROM Vector Table (continued)
Vector Address or Location in Boot
0x00000014
0x00000018
0x0000001C – 0x00000028
0x0000002C
0x00000030
0x00000034
0x00000038
0X0000003C
0x00000040
0x00000040 - 0x000001AC
Table 6-3. M-Boot ROM Version and Checksum Information
Copyright © 2012–2019, Texas Instruments Incorporated
ROM
IntDefaultHandler
IntDefaultHandler
Reserved (0x00000000)
IntDefaultHandler
IntDefaultHandler
Reserved (0x00000000)
IntDefaultHandler
SysTickIntHandler
GPIOIntHandler
IntDefaultHandler
Contents
Revision No = 0x0100
Revision Date = 0x1012 (Month / Year) = Oct 2012
Checksum
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Contents (Handler address)
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