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Memory Regions, Types and Attributes
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see the Memory Protection Unit (MPU) section in the Cortex-M3 Peripherals chapter.
Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target
addresses.
24.6.3 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding
memory transactions for the following reasons:
•
The processor can reorder some memory accesses to improve efficiency, providing this does not affect
the behavior of the instruction sequence.
•
The processor has multiple bus interfaces.
•
Memory or devices in the memory map have different wait states.
•
Some memory accesses are buffered or speculative.
Section 24.6.1
describes the cases where the memory system guarantees the order of memory accesses.
Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions
to force that ordering. The processor has the following memory barrier instructions:
•
The data memory barrier (DMB) instruction ensures that outstanding memory transactions complete
before subsequent memory transactions.
•
The data synchronization barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
•
The instruction synchronization barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
•
MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction, use
a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context
switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming
the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If
the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not
required.
•
Vector table If the program changes an entry in the vector table and then enables the corresponding
exception, use a DMB instruction between the operations. The DMB instruction ensures that if the
exception is taken immediately after being enabled, the processor uses the new exception vector.
•
Self-modifying codeIf a program contains self-modifying code, use an ISB instruction immediately after
the code modification in the program. The ISB instruction ensures subsequent instruction execution
uses the updated program.
•
Memory map switchingIf the system contains a memory map switching mechanism, use a DSB
instruction after switching the memory map in the program. The DSB instruction ensures subsequent
instruction execution uses the updated memory map.
•
Dynamic exception priority changeWhen an exception priority has to change when the exception is
pending or active, use DSB instructions after the change. The change then takes effect on completion
of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use
of DMB instructions.
For more information on the memory barrier instructions, see the Cortexâ„¢-M3 Instruction Set Technical
User's Manual.
1580
Cortex-M3 Processor
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
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