Set The Srg Clock Divide-Down Value; Set The Srg Clock Synchronization Mode; Set The Srg Clock Mode (Choose An Input Clock); Register Bits Used To Set The Sample Rate Generator (Srg) Clock Divide-Down Value - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com

15.8.19 Set the SRG Clock Divide-Down Value

Table 15-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value
Register Bit
SRGR1 7-0
15.8.19.1 Sample Rate Generator Clock Divider
The first divider stage generates the serial data bit clock from the input clock. This divider stage utilizes a
counter, preloaded by CLKGDV, that contains the divide ratio value.
The output of the first divider stage is the data bit clock, which is output as CLKG and which serves as the
input for the second and third stages of the divider.
CLKG has a frequency equal to 1/(CLKGDV + 1) of sample rate generator input clock. Thus, the sample
generator input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal
to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide-down,
the high-state duration is p + 1 cycles and the low-state duration is p cycles.

15.8.20 Set the SRG Clock Synchronization Mode

For more details on using the clock synchronization feature, see
Rate Generator Outputs to an External Clock.
Table 15-44. Register Bit Used to Set the SRG Clock Synchronization Mode
Register Bit
SRGR2 15

15.8.21 Set the SRG Clock Mode (Choose an Input Clock)

Table 15-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
Register Bit
PCR 7
SRGR2 13
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Name Function
CLKGDV Sample rate generator clock divide-down value
The input clock of the sample rate generator is divided by
(CLKGDV + 1) to generate the required sample rate generator
clock frequency. The default value of CLKGDV is 1 (divide input
clock by 2).
Name Function
GSYNC Sample rate generator clock synchronization
GSYNC is used only when the input clock source for the sample rate
generator is external—on the MCLKR or MCLKX pin.
GSYNC = 0
GSYNC = 1
Name Function
SCLKME Sample rate generator clock mode
CLKSM
SCLKME = 0
CLKSM = 0
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.4.3, Synchronizing Sample
The sample rate generator clock (CLKG) is free
running. CLKG oscillates without adjustment, and
FSG pulses every (FPER + 1) CLKG cycles.
Clock synchronization is performed. When a
pulse is detected on the FSR pin:
• CLKG is adjusted as necessary so that it is
synchronized with the input clock on the
MCLKR or MCLKX pin.
• FSG pulses. FSG only pulses in response to
a pulse on the FSR pin. The frame-
synchronization period defined in FPER is
ignored.
Reserved
C28 Multichannel Buffered Serial Port (McBSP)
Receiver Configuration
Type Reset Value
R/W 0000 0001
Reset
Type Value
R/W 0
Reset
Type Value
R/W 0
R/W 1
1095